static void slimport_main_proc(struct anx7808_data *anx7808)
{
mutex_lock(&anx7808->lock);
if (!sp_tx_pd_mode) {
sp_tx_int_irq_handler();
hdmi_rx_int_irq_handler();
}
if (sp_tx_system_state == STATE_CABLE_PLUG)
slimport_cable_plug_proc(anx7808);
if (sp_tx_system_state == STATE_PARSE_EDID)
slimport_edid_proc();
if (anx7808->update_chg_type && !sp_tx_pd_mode) {
sp_tx_chg_current_ma = sp_tx_get_chg_current();
anx7808->update_chg_type = false;
complete_all(&init_aux_ch_completion);
}
if (sp_tx_system_state == STATE_CONFIG_HDMI)
sp_tx_config_hdmi_input();
if (sp_tx_system_state == STATE_LINK_TRAINING) {
if (!sp_tx_lt_pre_config())
sp_tx_hw_link_training();
}
if (sp_tx_system_state == STATE_CONFIG_OUTPUT)
slimport_config_output();
if (sp_tx_system_state == STATE_HDCP_AUTH) {
if (hdcp_enable) {
sp_tx_hdcp_process();
} else {
sp_tx_power_down(SP_TX_PWR_HDCP);
sp_tx_video_mute(0);
hdmi_rx_show_video_info();
sp_tx_show_infomation();
sp_tx_set_sys_state(STATE_PLAY_BACK);
}
}
if (sp_tx_system_state == STATE_PLAY_BACK)
slimport_playback_proc();
mutex_unlock(&anx7808->lock);
}
static void slimport_main_proc(struct anx7808_data *anx7808)
{
mutex_lock(&anx7808->lock);
if (!sp_tx_pd_mode) {
sp_tx_int_irq_handler();
hdmi_rx_int_irq_handler();
}
if (sp_tx_system_state == STATE_CABLE_PLUG)
slimport_cable_plug_proc(anx7808);
if (sp_tx_system_state == STATE_PARSE_EDID)
slimport_edid_proc();
if (sp_tx_system_state == STATE_CONFIG_HDMI)
sp_tx_config_hdmi_input();
if (sp_tx_system_state == STATE_LINK_TRAINING) {
if (!sp_tx_lt_pre_config())
sp_tx_hw_link_training();
}
if (sp_tx_system_state == STATE_CONFIG_OUTPUT)
slimport_config_output();
if (sp_tx_system_state == STATE_HDCP_AUTH) {
if (hdcp_enable) {
sp_tx_hdcp_process();
} else {
sp_tx_power_down(SP_TX_PWR_HDCP);
sp_tx_video_mute(0);
sp_tx_show_infomation();
sp_tx_set_sys_state(STATE_PLAY_BACK);
}
}
if (sp_tx_system_state == STATE_PLAY_BACK)
slimport_playback_proc();
#ifdef CONFIG_CHARGER_SMB345
slimport_cable_monitor(anx7808);
#endif
mutex_unlock(&anx7808->lock);
}
static void slimport_main_proc(struct anx7808_data *anx7808)
{
//unchar c1, c2;
///printk("=================slimport_main_proc================\n");
mutex_lock(&anx7808->lock);
//ASUS BSP Wei Lai +++
//sp_tx_chip_located();
///printk("(1) slimport_main_proc \n");
//sp_tx_hardware_poweron(anx7808_client);
//msleep(200);
//ASUS BSP Wei Lai ---
if (!sp_tx_pd_mode) {
/// printk("(1-1)slimport_main_proc \n");
sp_tx_int_irq_handler();
hdmi_rx_int_irq_handler();
/// printk("(1-2)slimport_main_proc \n");
}
//sp_tx_hardware_chip_enable(anx7808_client);
//printk("=================slimport_main_proc END================\n");
///printk("(2)slimport_main_proc \n");
if (sp_tx_system_state == STATE_CABLE_PLUG)
slimport_cable_plug_proc(anx7808);
///printk("(3)slimport_main_proc \n");
if (sp_tx_system_state == STATE_PARSE_EDID)
slimport_edid_proc();
//ANX +++: (ver0.4)
if (sp_tx_system_state == STATE_CONFIG_HDMI) {
// if((sp_tx_asus_pad) && (!myDP_DP_Dongle))
if(sp_tx_asus_pad)
{
int try_count= 50;
while (try_count) {
if (!sp_tx_config_hdmi_input())
break;
else
msleep(20);
try_count --;
};
printk("[myDP] try_count = %d\n", try_count);
if ( (!check_mdp4_dtv() || !try_count) && (g_slimport_bypass_check_mdp4) )
{
printk("[myDP] after check RX input, still TMDS not ready, go link , then power down\n");
sp_tx_set_sys_state(STATE_LINK_TRAINING);
}
else
{
printk("[myDP] TMDS ready, go to next process\n");
g_slimport_bypass_check_mdp4 = 1;
}
if (sp_tx_system_state == STATE_LINK_TRAINING)
sp_tx_sw_error_power_down();
else
sp_tx_config_hdmi_pad();
}
else
{
if (sp_tx_rx_type == RX_VGA)
{
// check need under 480p
if (myDP_check_7808_rx_under_480p())
{
sp_tx_config_hdmi_input();
}
}
else
{
sp_tx_config_hdmi_input();
}
}
}
if (sp_tx_system_state == STATE_LINK_TRAINING) {
if (!sp_tx_asus_pad) {
if (!sp_tx_lt_pre_config())
sp_tx_hw_link_training();
}
else
{// pad mode not do link training, so power down chip
sp_tx_sw_error_power_down();
}
}
//ANX ---: (ver0.4)
//printk("=================slimport_main_proc================\n");
//printk("=================slimport_main_proc END================\n");
if (sp_tx_system_state == STATE_CONFIG_OUTPUT)
slimport_config_output();
if (sp_tx_system_state == STATE_HDCP_AUTH) {
if (hdcp_enable &&
((sp_tx_rx_type == RX_HDMI) ||
( sp_tx_rx_type ==RX_DP) || ( sp_tx_rx_type ==RX_VGA)) ) {
//ANX +++: (ver:20130105) pad solution
// if((sp_tx_asus_pad) && (!myDP_DP_Dongle))
if(sp_tx_asus_pad)
sp_tx_sw_hdcp_process();
else
sp_tx_hdcp_process();
//ANX ---: (ver:20130105) pad solution
} else {
sp_tx_power_down(SP_TX_PWR_HDCP);
sp_tx_video_mute(0);
sp_tx_show_infomation();
sp_tx_set_sys_state(STATE_PLAY_BACK);
}
}
if (sp_tx_system_state == STATE_PLAY_BACK)
slimport_playback_proc();
//ASUS BSP Wei Lai +++
//sp_tx_hardware_powerdown(anx7808_client);
//ASUS BSP Wei Lai ---
mutex_unlock(&anx7808->lock);
/// printk("=================slimport_main_proc END================\n");
}
static void slimport_playback_proc(void)
{
unchar c1 = 0;
unchar c=0;
unchar c2=0;
if (g_dump_7808_reg)
{
//0x7E, 8B
dump_7808_reg_info();
// dump_7808_reg_pclk();
sp_tx_show_infomation();
}
if (g_dump_7730_reg)
{
sp_tx_link_err_check_1();
sp_read_reg(TX_P2, SP_TX_TOTAL_PIXEL_STA_L, &c);
sp_read_reg(TX_P2, SP_TX_TOTAL_PIXEL_STA_H, &c1);
if(c1!=0x7||c!=0xd0)
printk("ANX7808 TX cur_h_res = 0x%x,0x%x\n", c,c1);
sp_read_reg(TX_P2, SP_TX_TOTAL_LINE_STA_L, &c);
sp_read_reg(TX_P2, SP_TX_TOTAL_LINE_STA_H, &c1);
if(c1!=0x4||c!=0xd3)
printk("ANX7808 TX cur_v_res = 0x%x\n,0x%x\n", c,c1);
if ( (sp_tx_asus_pad) && (!myDP_DP_Dongle) )
{
//========================================
// disable 7730 OCM
i2c_master_write_reg(7,0xf0, 0);
i2c_master_read_reg(7,0xf0, &c);
if(c != 0 )
i2c_master_write_reg(7,0xf0, 0);
//========================================
i2c_master_read_reg(0, 0xcb, &c1);
i2c_master_read_reg(1, 0xd1, &c);
//i2c_master_read_reg(0, 0x31, &c2);
i2c_master_write_reg(0, 0xcb, c1);
i2c_master_write_reg(1, 0xd1, c);
if ((c1 & 0x08) || (c & 0x80))
{
printk("[myDP] # 7730 video FIFO error , 0xcb= (%x), RX ISR6 = (%x)\n", c1, c);
}
// printk("========== ANX7730 reg 0x50 DUMP ============\n");
/*
for (i=0x20; i <=0x30; i++)
{
i2c_master_read_reg(0, i , &c);
if (i%0xf)
printk("0x%x = (%x), ", i, c);
else
printk("0x%x = (%x)\n", i, c);
}
*/
i2c_master_read_reg(0, 0x24 , &c1);
i2c_master_read_reg(0, 0x25 , &c2);
if ((c1 != 0x7) || (c2 != 0xd0))
{
printk("Fail 7730 0x50 H total = (%x, %x)", c1, c2);
}
// printk("========== ANX7730 reg 0x72 DUMP ============\n");
/*
for (i=0x24; i <=0x34; i++)
{
i2c_master_read_reg(5, i , &c);
if (i%0xf)
printk("0x%x = (%x), ", i, c);
else
printk("0x%x = (%x)\n", i, c);
}
*/
i2c_master_read_reg(5, 0x2b , &c1);
i2c_master_read_reg(5, 0x2c , &c2);
if ((c1 != 0xd0) || (c2 != 0x7))
{
printk("Fail 7730 0x72 H total = (%x, %x)", c1, c2);
}
//
//========================================
// re-enable 7730 OCM
i2c_master_write_reg(7,0xf0, 0xe6);
i2c_master_write_reg(7,0xf0, 0xe6);
//========================================
}
}
}
