void kw2xrf_read_fifo(uint8_t *data, uint8_t length)
{
kw2xrf_spi_transfer_head();
spi_transfer_regs(kw2xrf_spi, MKW2XDRF_BUF_READ, NULL,
(char *)data, length);
kw2xrf_spi_transfer_tail();
}
/**
* @brief Read sequential registers from the LIS3DH.
*
* @param[in] dev Device descriptor
* @param[in] reg The source register starting address
* @param[in] len Number of bytes to read
* @param[out] buf The values of the source registers will be written here
*
* @return 0 on success
* @return -1 on error
*/
static int lis3dh_read_regs(const lis3dh_t *dev, const lis3dh_reg_t reg, const uint8_t len,
uint8_t *buf)
{
/* Set READ MULTIPLE mode */
uint8_t addr = (reg & LIS3DH_SPI_ADDRESS_MASK) | LIS3DH_SPI_READ_MASK | LIS3DH_SPI_MULTI_MASK;
/* Acquire exclusive access to the bus. */
spi_acquire(dev->spi);
/* Perform the transaction */
gpio_clear(dev->cs);
if (spi_transfer_regs(dev->spi, addr, NULL, (char *)buf, len) < 0) {
/* Transfer error */
gpio_set(dev->cs);
/* Release the bus for other threads. */
spi_release(dev->spi);
return -1;
}
gpio_set(dev->cs);
/* Release the bus for other threads. */
spi_release(dev->spi);
return 0;
}
int lis3dh_read_xyz(const lis3dh_t *dev, lis3dh_data_t *acc_data)
{
uint8_t i;
/* Set READ MULTIPLE mode */
static const uint8_t addr = (LIS3DH_REG_OUT_X_L | LIS3DH_SPI_READ_MASK | LIS3DH_SPI_MULTI_MASK);
/* Acquire exclusive access to the bus. */
spi_acquire(dev->spi);
/* Perform the transaction */
gpio_clear(dev->cs);
if (spi_transfer_regs(dev->spi, addr, NULL, (char *)acc_data,
sizeof(lis3dh_data_t)) != sizeof(lis3dh_data_t)) {
/* Transfer error */
gpio_set(dev->cs);
/* Release the bus for other threads. */
spi_release(dev->spi);
return -1;
}
gpio_set(dev->cs);
/* Release the bus for other threads. */
spi_release(dev->spi);
/* Scale to milli-G */
for (i = 0; i < 3; ++i) {
int32_t tmp = (int32_t)(((int16_t *)acc_data)[i]);
tmp *= dev->scale;
tmp /= 32768;
(((int16_t *)acc_data)[i]) = (int16_t)tmp;
}
return 0;
}
void kw2xrf_write_fifo(uint8_t *data, uint8_t length)
{
kw2xrf_spi_transfer_head();
spi_transfer_regs(kw2xrf_spi, MKW2XDRF_BUF_WRITE,
(char *)data, NULL, length);
kw2xrf_spi_transfer_tail();
}
static uint8_t cmd_rcr_miimac(enc28j60_t *dev, uint8_t reg, int8_t bank)
{
char res[2];
switch_bank(dev, bank);
gpio_clear(dev->cs_pin);
spi_transfer_regs(dev->spi, CMD_RCR | reg, NULL, res, 2);
gpio_set(dev->cs_pin);
return (uint8_t)res[1];
}
/**
* @brief Write a register value to the sensor
*
* @param[in] dev device descriptor
* @param[in] addr register address
* @param[in] len register size
* @param[in] buf source buffer
*/
static void ds3234_write_reg(const ds3234_params_t *dev, uint8_t addr, size_t len, const uint8_t *buf)
{
uint8_t command = DS3234_CMD_WRITE | addr;
/* Acquire exclusive access to the bus. */
spi_acquire(dev->spi, dev->cs, SPI_MODE_3, dev->clk);
/* Perform the transaction */
spi_transfer_regs(dev->spi, dev->cs, command, buf, NULL, len);
/* Release the bus for other threads. */
spi_release(dev->spi);
}
uint16_t cc2420_reg_read(const cc2420_t *dev, const uint8_t addr)
{
network_uint16_t tmp;
spi_acquire(SPI_BUS, SPI_CS, SPI_MODE, SPI_CLK);
spi_transfer_regs(SPI_BUS, SPI_CS, (CC2420_REG_READ | addr),NULL, &tmp, 2);
spi_release(SPI_BUS);
return byteorder_ntohs(tmp);
}
void cc2420_reg_write(const cc2420_t *dev,
const uint8_t addr,
const uint16_t value)
{
uint16_t tmp = byteorder_htons(value).u16;
spi_acquire(SPI_BUS, SPI_CS, SPI_MODE, SPI_CLK);
spi_transfer_regs(SPI_BUS, SPI_CS, (CC2420_REG_WRITE | addr), &tmp, NULL, 2);
spi_release(SPI_BUS);
}
void cc110x_writeburst_reg(uint8_t addr, char *src, uint8_t count)
{
unsigned int cpsr;
spi_acquire(CC110X_SPI);
cpsr = disableIRQ();
cc110x_cs();
spi_transfer_regs(CC110X_SPI, addr | CC1100_WRITE_BURST, src, 0, count);
gpio_set(CC110X_CS);
restoreIRQ(cpsr);
spi_release(CC110X_SPI);
}
void cc110x_writeburst_reg(cc110x_t *dev, uint8_t addr, const char *src, uint8_t count)
{
unsigned int cpsr;
spi_acquire(dev->params.spi);
cpsr = disableIRQ();
cc110x_cs(dev);
spi_transfer_regs(dev->params.spi, addr | CC110X_WRITE_BURST, (char *)src, 0, count);
gpio_set(dev->params.cs);
restoreIRQ(cpsr);
spi_release(dev->params.spi);
}
int nrf24l01p_read_payload(const nrf24l01p_t *dev, char *answer, unsigned int size)
{
/* Acquire exclusive access to the bus. */
spi_acquire(dev->spi, dev->cs, SPI_MODE, SPI_CLK);
spi_transfer_regs(dev->spi, dev->cs, CMD_R_RX_PAYLOAD, NULL, answer, size);
xtimer_spin(DELAY_AFTER_FUNC_TICKS);
/* Release the bus for other threads. */
spi_release(dev->spi);
return 0;
}
int nrf24l01p_preload(const nrf24l01p_t *dev, char *data, unsigned int size)
{
size = (size <= 32) ? size : 32;
/* Acquire exclusive access to the bus. */
spi_acquire(dev->spi, dev->cs, SPI_MODE, SPI_CLK);
spi_transfer_regs(dev->spi, dev->cs, CMD_W_TX_PAYLOAD, data, NULL, size);
/* Release the bus for other threads. */
spi_release(dev->spi);
xtimer_spin(DELAY_AFTER_FUNC_TICKS);
return 0;
}
/**
* @brief Read a register from the sensor
*
* @param[in] dev device descriptor
* @param[in] addr register address
* @param[in] len register size
* @param[out] buf destination buffer
*
* @return 0 on success
* @return -1 on communication errors
*/
static int adt7310_read_reg(const adt7310_t *dev, const uint8_t addr, const uint8_t len,
uint8_t *buf)
{
int status = 0;
uint8_t command = ADT7310_CMD_READ | (addr << ADT7310_CMD_ADDR_SHIFT);
/* Acquire exclusive access to the bus. */
spi_acquire(dev->spi, dev->cs, SPI_MODE_0, dev->clk);
/* Perform the transaction */
spi_transfer_regs(dev->spi, dev->cs, command, NULL, buf, (size_t)len);
/* Release the bus for other threads. */
spi_release(dev->spi);
return status;
}
int nrf24l01p_set_tx_address(const nrf24l01p_t *dev, const char *saddr, unsigned int length)
{
/* Acquire exclusive access to the bus. */
spi_acquire(dev->spi, dev->cs, SPI_MODE, SPI_CLK);
spi_transfer_regs(dev->spi, dev->cs,
(CMD_W_REGISTER | (REGISTER_MASK & REG_TX_ADDR)),
saddr, NULL, length);
/* Release the bus for other threads. */
spi_release(dev->spi);
xtimer_spin(DELAY_AFTER_FUNC_TICKS);
return (int)length;
}
int nrf24l01p_read_payload(nrf24l01p_t *dev, char *answer, unsigned int size)
{
int status;
/* Acquire exclusive access to the bus. */
spi_acquire(dev->spi);
gpio_clear(dev->cs);
xtimer_spin(DELAY_CS_TOGGLE_TICKS);
status = spi_transfer_regs(dev->spi, CMD_R_RX_PAYLOAD, 0, answer, size);
xtimer_spin(DELAY_CS_TOGGLE_TICKS);
gpio_set(dev->cs);
xtimer_spin(DELAY_AFTER_FUNC_TICKS);
/* Release the bus for other threads. */
spi_release(dev->spi);
return status;
}
static int nvram_spi_write(nvram_t *dev, uint8_t *src, uint32_t dst, size_t len)
{
nvram_spi_params_t *spi_dev = (nvram_spi_params_t *) dev->extra;
int status;
union {
uint32_t u32;
char c[4];
} addr;
/* Address is expected by the device as big-endian, i.e. network byte order,
* we utilize the network byte order macros here. */
addr.u32 = HTONL(dst);
/* Acquire exclusive bus access */
spi_acquire(spi_dev->spi);
/* Assert CS */
gpio_clear(spi_dev->cs);
/* Enable writes */
status = spi_transfer_byte(spi_dev->spi, NVRAM_SPI_CMD_WREN, NULL);
if (status < 0)
{
return status;
}
/* Release CS */
gpio_set(spi_dev->cs);
xtimer_spin(NVRAM_SPI_CS_TOGGLE_TICKS);
/* Re-assert CS */
gpio_clear(spi_dev->cs);
/* Write command and address */
status = spi_transfer_regs(spi_dev->spi, NVRAM_SPI_CMD_WRITE,
&addr.c[sizeof(addr.c) - spi_dev->address_count], NULL,
spi_dev->address_count);
if (status < 0)
{
return status;
}
/* Keep holding CS and write data */
status = spi_transfer_bytes(spi_dev->spi, (char *)src, NULL, len);
if (status < 0)
{
return status;
}
/* Release CS */
gpio_set(spi_dev->cs);
/* Release exclusive bus access */
spi_release(spi_dev->spi);
return status;
}
int nrf24l01p_set_tx_address(nrf24l01p_t *dev, char *saddr, unsigned int length)
{
int status;
/* Acquire exclusive access to the bus. */
spi_acquire(dev->spi);
gpio_clear(dev->cs);
xtimer_spin(DELAY_CS_TOGGLE_TICKS);
status = spi_transfer_regs(dev->spi, (CMD_W_REGISTER | (REGISTER_MASK & REG_TX_ADDR)), saddr, NULL, length); /* address width is 5 byte */
xtimer_spin(DELAY_CS_TOGGLE_TICKS);
gpio_set(dev->cs);
/* Release the bus for other threads. */
spi_release(dev->spi);
xtimer_spin(DELAY_AFTER_FUNC_TICKS);
return status;
}
void kw2xrf_read_iregs(uint8_t addr, uint8_t *buf, uint8_t length)
{
if (length > (KW2XRF_IBUF_LENGTH - 1)) {
length = KW2XRF_IBUF_LENGTH - 1;
}
ibuf[0] = addr;
kw2xrf_spi_transfer_head();
spi_transfer_regs(kw2xrf_spi, MKW2XDM_IAR_INDEX | MKW2XDRF_REG_READ,
(char *)ibuf, (char *)ibuf, length + 1);
kw2xrf_spi_transfer_tail();
for (uint8_t i = 0; i < length; i++) {
buf[i] = ibuf[i + 1];
}
return;
}
void kw2xrf_write_iregs(uint8_t addr, uint8_t *buf, uint8_t length)
{
if (length > (KW2XRF_IBUF_LENGTH - 1)) {
length = KW2XRF_IBUF_LENGTH - 1;
}
ibuf[0] = addr;
for (uint8_t i = 0; i < length; i++) {
ibuf[i + 1] = buf[i];
}
kw2xrf_spi_transfer_head();
spi_transfer_regs(kw2xrf_spi, MKW2XDM_IAR_INDEX,
(char *)ibuf, NULL, length + 1);
kw2xrf_spi_transfer_tail();
return;
}
/**
* @brief Read a register from the sensor
*
* @param[in] dev device descriptor
* @param[in] addr register address
* @param[in] len register size
* @param[out] buf destination buffer
*
* @return 0 on success
* @return -1 on communication errors
*/
static int adt7310_read_reg(const adt7310_t *dev, const uint8_t addr, const uint8_t len,
uint8_t *buf)
{
int status = 0;
uint8_t command = ADT7310_CMD_READ | (addr << ADT7310_CMD_ADDR_SHIFT);
/* Acquire exclusive access to the bus. */
spi_acquire(dev->spi);
/* Perform the transaction */
gpio_clear(dev->cs);
if (spi_transfer_regs(dev->spi, command, NULL, (char *)buf, len) < len) {
status = -1;
}
gpio_set(dev->cs);
/* Release the bus for other threads. */
spi_release(dev->spi);
return status;
}
int nrf24l01p_preload(nrf24l01p_t *dev, char *data, unsigned int size)
{
int status;
size = (size <= 32) ? size : 32;
/* Acquire exclusive access to the bus. */
spi_acquire(dev->spi);
gpio_clear(dev->cs);
xtimer_spin(DELAY_CS_TOGGLE_TICKS);
status = spi_transfer_regs(dev->spi, CMD_W_TX_PAYLOAD, data, NULL, size);
xtimer_spin(DELAY_CS_TOGGLE_TICKS);
gpio_set(dev->cs);
/* Release the bus for other threads. */
spi_release(dev->spi);
xtimer_spin(DELAY_AFTER_FUNC_TICKS);
return status;
}
/**
* @print register
*/
void print_register(char reg, int num_bytes)
{
vtimer_init();
char buf_return[num_bytes];
int ret;
gpio_clear(CS_PIN);
vtimer_usleep(1);
ret = spi_transfer_regs(SPI_PORT, (CMD_R_REGISTER | (REGISTER_MASK & reg)), 0, buf_return, num_bytes);
gpio_set(CS_PIN);
if (ret < 0) {
printf("Error in read access\n");
}
else {
if (num_bytes < 2) {
printf("0x%x returned: ", reg);
for (int i = 0; i < num_bytes; i++) {
prtbin(buf_return[i]);
}
}
else {
printf("0x%x returned: ", reg);
for (int i = 0; i < num_bytes; i++) {
printf("%x ", buf_return[i]);
}
printf("\n\n");
}
}
}
static int nvram_spi_read(nvram_t *dev, uint8_t *dst, uint32_t src, size_t len)
{
nvram_spi_params_t *spi_dev = (nvram_spi_params_t *) dev->extra;
int status;
union {
uint32_t u32;
char c[4];
} addr;
/* Address is expected by the device as big-endian, i.e. network byte order,
* we utilize the network byte order macros here. */
addr.u32 = HTONL(src);
/* Acquire exclusive bus access */
spi_acquire(spi_dev->spi);
/* Assert CS */
gpio_clear(spi_dev->cs);
/* Write command and address */
status = spi_transfer_regs(spi_dev->spi, NVRAM_SPI_CMD_READ,
&addr.c[sizeof(addr.c) - spi_dev->address_count],
NULL, spi_dev->address_count);
if (status < 0)
{
return status;
}
/* Keep holding CS and read data */
status = spi_transfer_bytes(spi_dev->spi, NULL, (char *)dst, len);
if (status < 0)
{
return status;
}
/* Release CS */
gpio_set(spi_dev->cs);
/* Release exclusive bus access */
spi_release(spi_dev->spi);
/* status contains the number of bytes actually read from the SPI bus. */
return status;
}
static void cmd_wbm(enc28j60_t *dev, uint8_t *data, size_t len)
{
gpio_clear(dev->cs_pin);
spi_transfer_regs(dev->spi, CMD_WBM, (char *)data, NULL, len);
gpio_set(dev->cs_pin);
}
