platform_result_t platform_spifi_init( const platform_spifi_t* spifi )
{
uint32_t spifiBaseClockRate;
uint32_t maxSpifiClock;
/*
if( spi_ptr->semaphore_is_inited == WICED_FALSE )
{
host_rtos_init_semaphore( &spi_ptr->in_use_semaphore );
spi_ptr->semaphore_is_inited = WICED_TRUE;
}
else
{
host_rtos_get_semaphore( &spi_ptr->in_use_semaphore, NEVER_TIMEOUT, WICED_FALSE );
}
*/
/* Mux the port and pin to direct it to SPIFI */
platform_pin_set_alternate_function( &spifi->clock );
platform_pin_set_alternate_function( &spifi->miso );
platform_pin_set_alternate_function( &spifi->mosi );
platform_pin_set_alternate_function( &spifi->sio2 );
platform_pin_set_alternate_function( &spifi->sio3 );
platform_pin_set_alternate_function( &spifi->cs );
/* SPIFI base clock will be based on the main PLL rate and a divider */
spifiBaseClockRate = Chip_Clock_GetClockInputHz(CLKIN_MAINPLL);
/* Setup SPIFI clock to run around 1Mhz. Use divider E for this, as it allows
* higher divider values up to 256 maximum)
*/
Chip_Clock_SetDivider(CLK_IDIV_E, CLKIN_MAINPLL, ((spifiBaseClockRate / 1000000) + 1));
Chip_Clock_SetBaseClock(CLK_BASE_SPIFI, CLKIN_IDIVE, true, false);
/* Initialize LPCSPIFILIB library, reset the interface */
spifiInit( ( uint32_t )spifi->spifi_base, true);
/* register support for the family(s) we may want to work with */
spifiRegisterFamily( SPIFI_REG_FAMILY_MacronixMX25L );
/* Initialize and detect a device and get device context */
spifi_handle = spifiInitDevice( &lmem, sizeof(lmem), ( uint32_t ) spifi->spifi_base, SPIFLASH_BASE_ADDRESS );
/* Get some info needed for the application */
maxSpifiClock = spifiDevGetInfo(spifi_handle, SPIFI_INFO_MAXCLOCK);
/* Setup SPIFI clock to at the maximum interface rate the detected device
can use. This should be done after device init. */
Chip_Clock_SetDivider(CLK_IDIV_E, CLKIN_MAINPLL, ((spifiBaseClockRate / maxSpifiClock) + 1));
/* start by unlocking the device */
if (spifiDevUnlockDevice(spifi_handle) != SPIFI_ERR_NONE) {
return WICED_ERROR;
}
/* Enable quad. If not supported it will be ignored */
spifiDevSetOpts(spifi_handle, SPIFI_OPT_USE_QUAD, true);
/* Enter memMode */
spifiDevSetMemMode(spifi_handle, true);
/* Just a test */
maxSpifiClock = *( (uint32_t *)SPIFLASH_BASE_ADDRESS );
return spifi_handle == NULL ? WICED_ERROR : WICED_SUCCESS;
}
static void RunExample(void)
{
uint32_t spifiBaseClockRate;
uint32_t maxSpifiClock;
uint16_t libVersion;
SPIFI_HANDLE_T *pSpifi;
/* Report the library version to start with */
libVersion = spifiGetLibVersion();
DEBUGOUT("\r\n\r\nSPIFI Lib Version %02d%02d\r\n", ((libVersion >> 8) & 0xff), (libVersion & 0xff));
/* set the blink rate to 1/2 second while testing */
test_suiteSetErrorBlinkRate(500);
/* Setup SPIFI FLASH pin muxing (QUAD) */
Chip_SCU_SetPinMuxing(spifipinmuxing, sizeof(spifipinmuxing) / sizeof(PINMUX_GRP_T));
/* SPIFI base clock will be based on the main PLL rate and a divider */
spifiBaseClockRate = Chip_Clock_GetClockInputHz(CLKIN_MAINPLL);
/* Setup SPIFI clock to run around 1Mhz. Use divider E for this, as it allows
higher divider values up to 256 maximum) */
Chip_Clock_SetDivider(CLK_IDIV_E, CLKIN_MAINPLL, ((spifiBaseClockRate / 1000000) + 1));
Chip_Clock_SetBaseClock(CLK_BASE_SPIFI, CLKIN_IDIVE, true, false);
DEBUGOUT("SPIFI clock rate %d\r\n", Chip_Clock_GetClockInputHz(CLKIN_IDIVE));
/* initialize and get a handle to the spifi lib */
pSpifi = initializeSpifi();
/* Get some info needed for the application */
maxSpifiClock = spifiDevGetInfo(pSpifi, SPIFI_INFO_MAXCLOCK);
/* Get info */
DEBUGOUT("Device family = %s\r\n", spifiDevGetFamilyName(pSpifi));
DEBUGOUT("Capabilities = 0x%x\r\n", spifiDevGetInfo(pSpifi, SPIFI_INFO_CAPS));
DEBUGOUT("Device size = %d\r\n", spifiDevGetInfo(pSpifi, SPIFI_INFO_DEVSIZE));
DEBUGOUT("Max Clock Rate = %d\r\n", maxSpifiClock);
DEBUGOUT("Erase blocks = %d\r\n", spifiDevGetInfo(pSpifi, SPIFI_INFO_ERASE_BLOCKS));
DEBUGOUT("Erase block size = %d\r\n", spifiDevGetInfo(pSpifi, SPIFI_INFO_ERASE_BLOCKSIZE));
DEBUGOUT("Erase sub-blocks = %d\r\n", spifiDevGetInfo(pSpifi, SPIFI_INFO_ERASE_SUBBLOCKS));
DEBUGOUT("Erase sub-blocksize = %d\r\n", spifiDevGetInfo(pSpifi, SPIFI_INFO_ERASE_SUBBLOCKSIZE));
DEBUGOUT("Write page size = %d\r\n", spifiDevGetInfo(pSpifi, SPIFI_INFO_PAGESIZE));
DEBUGOUT("Max single readsize = %d\r\n", spifiDevGetInfo(pSpifi, SPIFI_INFO_MAXREADSIZE));
DEBUGOUT("Current dev status = 0x%x\r\n", spifiDevGetInfo(pSpifi, SPIFI_INFO_STATUS));
DEBUGOUT("Current options = %d\r\n", spifiDevGetInfo(pSpifi, SPIFI_INFO_OPTIONS));
/* Setup SPIFI clock to at the maximum interface rate the detected device
can use. This should be done after device init. */
Chip_Clock_SetDivider(CLK_IDIV_E, CLKIN_MAINPLL, ((spifiBaseClockRate / maxSpifiClock) + 1));
DEBUGOUT("SPIFI final Rate = %d\r\n", Chip_Clock_GetClockInputHz(CLKIN_IDIVE));
DEBUGOUT("\r\n");
/* Test the helper functions first */
test_suiteLibHelperBattery(pSpifi);
/* Now test the erase functions first in block mode, then in address mode */
test_suiteLibEraseBattery(pSpifi, false);
test_suiteLibEraseBattery(pSpifi, true);
/* test data integrity */
test_suiteDataBattery(pSpifi, false, false);
test_suiteDataBattery(pSpifi, true, false);
test_suiteDataBattery(pSpifi, true, true);
/* Done, de-init will enter memory mode */
spifiDevDeInit(pSpifi);
/* Indicate success */
DEBUGOUT("Complete.\r\n");
test_suiteSetErrorBlinkRate(0);
while (1) {
__WFI();
}
}