static int rk610_codec_mute(struct snd_soc_dai *dai, int mute) { struct snd_soc_codec *codec = dai->codec; struct rk610_codec_priv *rk610_codec =snd_soc_codec_get_drvdata(codec); printk("Enter::%s----%d--mute=%d\n",__FUNCTION__,__LINE__,mute); if (mute) { rk610_codec_write(codec,ACCELCODEC_R17, 0xFF); //AOL rk610_codec_write(codec,ACCELCODEC_R18, 0xFF); //AOR rk610_codec_write(codec,ACCELCODEC_R19, 0xFF); //AOM rk610_codec_write(codec,ACCELCODEC_R04, ASC_INT_MUTE_L|ASC_INT_MUTE_R|ASC_SIDETONE_L_OFF|ASC_SIDETONE_R_OFF); //soft mute //add for standby // if(!dai->capture_active) // { // rk610_codec_write(codec, ACCELCODEC_R1D, 0xFE); // rk610_codec_write(codec, ACCELCODEC_R1E, 0xFF); // rk610_codec_write(codec, ACCELCODEC_R1F, 0xFF); // } } else { // rk610_codec_write(codec,ACCELCODEC_R1D, 0x2a); //setup Vmid and Vref, other module power down // rk610_codec_write(codec,ACCELCODEC_R1E, 0x40); ///|ASC_PDASDML_ENABLE); rk610_codec_write(codec,ACCELCODEC_R17, Volume_Codec_PA|ASC_OUTPUT_ACTIVE|ASC_CROSSZERO_EN); //AOL Volume_Codec_PA|ASC_OUTPUT_ACTIVE|ASC_CROSSZERO_EN); //AOL rk610_codec_write(codec,ACCELCODEC_R18, Volume_Codec_PA|ASC_OUTPUT_ACTIVE|ASC_CROSSZERO_EN); //Volume_Codec_PA|ASC_OUTPUT_ACTIVE|ASC_CROSSZERO_EN); //AOR rk610_codec_write(codec,ACCELCODEC_R04, ASC_INT_ACTIVE_L|ASC_INT_ACTIVE_R|ASC_SIDETONE_L_OFF|ASC_SIDETONE_R_OFF); rk610_codec_write(codec,ACCELCODEC_R19, 0x7F); //AOM if(rk610_codec->pa_enable_time == 0) msleep(300); #if OUT_CAPLESS rk610_codec_write(codec,ACCELCODEC_R1F, 0x09|ASC_PDMIXM_ENABLE); #else rk610_codec_write(codec,ACCELCODEC_R1F, 0x09|ASC_PDMIXM_ENABLE|ASC_PDPAM_ENABLE); #endif // schedule_delayed_work(&rk610_codec->rk610_delayed_work, 0); // rk610_codec_reg_read(); if(rk610_codec->hdmi_ndet){ if(rk610_codec->pa_enable_time == 0 ) spk_ctrl_fun(GPIO_HIGH); else if(rk610_codec->pa_enable_time > 0 && rk610_codec->pa_enable_time < 300){ spk_ctrl_fun(GPIO_HIGH); msleep(rk610_codec->pa_enable_time) ; } else if(rk610_codec->pa_enable_time >=300 && rk610_codec->pa_enable_time < 1000) msleep(rk610_codec->pa_enable_time); } } return 0; }
static int rk610_codec_set_bias_level(struct snd_soc_codec *codec, enum snd_soc_bias_level level) { struct rk610_codec_priv *rk610_codec =snd_soc_codec_get_drvdata(codec); DBG("Enter::%s----%d now_level =%d old_level = %d\n",__FUNCTION__,__LINE__,level,codec->dapm.bias_level); switch (level) { case SND_SOC_BIAS_ON: break; case SND_SOC_BIAS_PREPARE: /* VREF, VMID=2x50k, digital enabled */ // rk610_codec_write(codec, ACCELCODEC_R1D, pwr_reg | 0x0080); break; case SND_SOC_BIAS_STANDBY: #if RESUME_PROBLEM if(rk610_codec->rk610_workstatus == SND_SOC_DAPM_STREAM_RESUME) { DBG("rk610 is resume,have not into standby\n"); rk610_codec->rk610_workstatus = SND_SOC_DAPM_STREAM_NOP; break; } #endif printk("rk610 standby\n"); spk_ctrl_fun(GPIO_LOW); rk610_codec_write(codec,ACCELCODEC_R0A, ASC_CLK_DISABLE); rk610_codec_write(codec, ACCELCODEC_R1D, 0xFE); rk610_codec_write(codec, ACCELCODEC_R1E, 0xFF); rk610_codec_write(codec, ACCELCODEC_R1F, 0xFF); break; case SND_SOC_BIAS_OFF: printk("rk610 power off\n"); spk_ctrl_fun(GPIO_LOW); rk610_codec_write(codec,ACCELCODEC_R0A, ASC_CLK_DISABLE); rk610_codec_write(codec, ACCELCODEC_R1D, 0xFF); rk610_codec_write(codec, ACCELCODEC_R1E, 0xFF); rk610_codec_write(codec, ACCELCODEC_R1F, 0xFF); break; } codec->dapm.bias_level = level; return 0; }
static void rk610_delayedwork_fun(struct work_struct *work) { struct snd_soc_codec *codec = rk610_codec_codec; DBG("--------%s----------\n",__FUNCTION__); spk_ctrl_fun(GPIO_HIGH); #if OUT_CAPLESS rk610_codec_write(codec,ACCELCODEC_R1F, 0x09|ASC_PDMIXM_ENABLE); #else rk610_codec_write(codec,ACCELCODEC_R1F, 0x09|ASC_PDMIXM_ENABLE|ASC_PDPAM_ENABLE); #endif }
static void rk610_delayedwork_fun(struct work_struct *work) { struct snd_soc_codec *codec = rk610_codec_codec; struct rk610_codec_priv *rk610_codec =snd_soc_codec_get_drvdata(codec); struct rk610_codec_platform_data *pdata= rk610_codec->pdata; DBG("--------%s----------\n",__FUNCTION__); if(!pdata->boot_depop){ #if OUT_CAPLESS rk610_codec_write(codec,ACCELCODEC_R1F, 0x09|ASC_PDMIXM_ENABLE); #else rk610_codec_write(codec,ACCELCODEC_R1F, 0x09|ASC_PDMIXM_ENABLE|ASC_PDPAM_ENABLE); #endif } spk_ctrl_fun(GPIO_HIGH); }
static ssize_t RK610_PROC_write(struct file *file, const char __user *buffer, unsigned long len, void *data) { char *cookie_pot; char *p; int reg; int value; cookie_pot = (char *)vmalloc( len ); if (!cookie_pot) { return -ENOMEM; } else { if (copy_from_user( cookie_pot, buffer, len )) return -EFAULT; } switch(cookie_pot[0]) { case 'p': spk_ctrl_fun(GPIO_HIGH); break; case 'o': spk_ctrl_fun(GPIO_LOW); break; case 'r': case 'R': printk("Read reg debug\n"); if(cookie_pot[1] ==':') { strsep(&cookie_pot,":"); while((p=strsep(&cookie_pot,","))) { reg = simple_strtol(p,NULL,16); value = rk610_codec_read(rk610_codec_codec,reg); printk("wm8994_read:0x%04x = 0x%04x\n",reg,value); } printk("\n"); } else { printk("Error Read reg debug.\n"); printk("For example: echo 'r:22,23,24,25'>wm8994_ts\n"); } break; case 'w': case 'W': printk("Write reg debug\n"); if(cookie_pot[1] ==':') { strsep(&cookie_pot,":"); while((p=strsep(&cookie_pot,"="))) { reg = simple_strtol(p,NULL,16); p=strsep(&cookie_pot,","); value = simple_strtol(p,NULL,16); rk610_codec_write(rk610_codec_codec,reg,value); printk("wm8994_write:0x%04x = 0x%04x\n",reg,value); } printk("\n"); } else { printk("Error Write reg debug.\n"); printk("For example: w:22=0,23=0,24=0,25=0\n"); } break; case 'D' : printk("Dump reg\n"); rk610_codec_reg_read(); break; } return len; }
static int rk610_codec_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt) { struct snd_soc_codec *codec = codec_dai->codec; struct rk610_codec_priv *rk610_codec =snd_soc_codec_get_drvdata(codec); u16 iface = 0; spk_ctrl_fun(GPIO_LOW); rk610_codec_write(codec,ACCELCODEC_R1D, 0x2a); //setup Vmid and Vref, other module power down rk610_codec_write(codec,ACCELCODEC_R1E, 0x40); ///|ASC_PDASDML_ENABLE); /* set master/slave audio interface */ switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { case SND_SOC_DAIFMT_CBM_CFM: iface = 0x0040; break; case SND_SOC_DAIFMT_CBS_CFS: iface = 0x0000; break; default: return -EINVAL; } /* interface format */ switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { case SND_SOC_DAIFMT_I2S: iface |= 0x0002; break; case SND_SOC_DAIFMT_RIGHT_J: break; case SND_SOC_DAIFMT_LEFT_J: iface |= 0x0001; break; case SND_SOC_DAIFMT_DSP_A: iface |= 0x0003; break; case SND_SOC_DAIFMT_DSP_B: iface |= 0x0013; break; default: return -EINVAL; } /* clock inversion */ switch (fmt & SND_SOC_DAIFMT_INV_MASK) { case SND_SOC_DAIFMT_NB_NF: break; case SND_SOC_DAIFMT_IB_IF: iface |= 0x0090; break; case SND_SOC_DAIFMT_IB_NF: iface |= 0x0080; break; case SND_SOC_DAIFMT_NB_IF: iface |= 0x0010; break; default: return -EINVAL; } DBG("Enter::%s----%d iface=%x\n",__FUNCTION__,__LINE__,iface); rk610_codec_write(codec, ACCELCODEC_R09, iface); return 0; }