void usb_phy_init(struct platform_device *_dev)
{
#ifdef CONFIG_USB_CORE_IP_293A
#if defined(CONFIG_ARCH_SCX35)
/*shark and dolphin are the same value with SPRD ref phone*/
#ifdef CONFIG_OF
struct device_node *np = _dev->dev.of_node;
if (of_property_read_u32(np, "tune_value", &tune_from_uboot))
{
pr_info("read tune_value error\n");
return -ENODEV;
}
pr_info("Usb_hw.c: [%s]usb phy tune from uboot: 0x%x\n", __FUNCTION__, tune_from_uboot);
#endif
__raw_writel(tune_from_uboot,REG_AP_APB_USB_PHY_TUNE);
//sci_glb_set(REG_AP_APB_USB_PHY_TUNE,BIT(9)|BIT(10)|BIT(11)|BIT(20));
#else
/*
* tiger PHY reg is different with previous ,
*7710 has the same core IP with tiger,but PHY reg also diff
*/
sprd_greg_set_bits(REG_TYPE_AHB_GLOBAL,BIT(11), USB_PHY_CTRL);
sprd_greg_set_bits(REG_TYPE_AHB_GLOBAL,BIT(10), USB_PHY_CTRL);
sprd_greg_set_bits(REG_TYPE_AHB_GLOBAL,BIT(20), USB_PHY_CTRL);
sprd_greg_set_bits(REG_TYPE_AHB_GLOBAL,BIT(9), USB_PHY_CTRL);
sprd_greg_clear_bits(REG_TYPE_AHB_GLOBAL,BIT(8), USB_PHY_CTRL);
sprd_greg_set_bits(REG_TYPE_AHB_GLOBAL,BIT(13), USB_PHY_CTRL);
sprd_greg_clear_bits(REG_TYPE_AHB_GLOBAL,BIT(12), USB_PHY_CTRL);
sprd_greg_clear_bits(REG_TYPE_AHB_GLOBAL,BIT(15)|BIT(14), USB_PHY_CTRL);
#endif
#else
if (sprd_greg_read(REG_TYPE_AHB_GLOBAL,CHIP_ID) == CHIP_ID_8810S){
/*SMIC chip id == 0x88100001*/
sprd_greg_clear_bits(REG_TYPE_AHB_GLOBAL,BIT(3)|BIT(2), USB_PHY_CTRL);
sprd_greg_set_bits(REG_TYPE_AHB_GLOBAL,BIT(1) | BIT(0), USB_PHY_CTRL);
sprd_greg_set_bits(REG_TYPE_AHB_GLOBAL,BIT(9), USB_PHY_CTRL);
sprd_greg_set_bits(REG_TYPE_AHB_GLOBAL,BIT(16), USB_PHY_CTRL);
sprd_greg_clear_bits(REG_TYPE_AHB_GLOBAL,BIT(17), USB_PHY_CTRL);
sprd_greg_clear_bits(REG_TYPE_AHB_GLOBAL,BIT(13), USB_PHY_CTRL);
sprd_greg_clear_bits(REG_TYPE_AHB_GLOBAL, BIT(12), USB_PHY_CTRL);
sprd_greg_clear_bits(REG_TYPE_AHB_GLOBAL,BIT(15)|BIT(14), USB_PHY_CTRL);
sprd_greg_write(REG_TYPE_AHB_GLOBAL,0x28,USB_SPR_REG);
}else{
/*
* config usb phy controller
*/
sprd_greg_set_bits(REG_TYPE_AHB_GLOBAL,BIT(8), USB_PHY_CTRL);
sprd_greg_set_bits(REG_TYPE_AHB_GLOBAL,BIT(17), USB_PHY_CTRL);
sprd_greg_clear_bits(REG_TYPE_AHB_GLOBAL,BIT(16), USB_PHY_CTRL);
sprd_greg_clear_bits(REG_TYPE_AHB_GLOBAL,BIT(13)|BIT(12), USB_PHY_CTRL);
sprd_greg_set_bits(REG_TYPE_AHB_GLOBAL,BIT(15)|BIT(14), USB_PHY_CTRL);
}
#endif
}
/**
* sdhci_sprd_set_base_clock - set base clock for SDIO module
* @host: sdio host to be set.
* @clock: The clock rate being requested.
*/
static void sdhci_sprd_set_base_clock(struct sdhci_host *host, unsigned int clock)
{
struct clk *clk_parent;
/* don't bother if the clock is going off. */
if (clock == 0)
return;
if (clock > SDIO_MAX_CLK)
clock = SDIO_MAX_CLK;
/* Select the clk source of SDIO, default is 96MHz */
if( !strcmp(host->hw_name, "Spread SDIO host0") ){
host->clk = clk_get(NULL, "clk_sdio0");
if (clock >= SDIO_BASE_CLK_96M) {
clk_parent = clk_get(NULL, "clk_96m");
} else if (clock >= SDIO_BASE_CLK_64M) {
clk_parent = clk_get(NULL, "clk_64m");
} else if (clock >= SDIO_BASE_CLK_48M) {
clk_parent = clk_get(NULL, "clk_48m");
} else {
clk_parent = clk_get(NULL, "clk_26m");
}
}else if( !strcmp(host->hw_name, "Spread SDIO host1") ){
host->clk = clk_get(NULL, "clk_sdio1");
if (clock >= SDIO_BASE_CLK_96M) {
clk_parent = clk_get(NULL, "clk_96m");
} else if (clock >= SDIO_BASE_CLK_64M) {
clk_parent = clk_get(NULL, "clk_64m");
} else if (clock >= SDIO_BASE_CLK_48M) {
clk_parent = clk_get(NULL, "clk_48m");
} else {
clk_parent = clk_get(NULL, "clk_26m");
}
}else if( !strcmp(host->hw_name, "Spread SDIO host2") ){
host->clk = clk_get(NULL, "clk_sdio2");
clk_parent = clk_get(NULL, "clk_96m");
}else if( !strcmp(host->hw_name, "Spread EMMC host0") ){
host->clk = clk_get(NULL, "clk_emmc0");
clk_parent = clk_get(NULL, "clk_26m");
}
clk_set_parent(host->clk, clk_parent);
pr_debug("after set sd clk, CLK_GEN5:0x%x\n", sprd_greg_read(REG_TYPE_GLOBAL, GR_CLK_GEN5));
return;
}
int mpll_calibrate(int cpu_freq)
{
u32 val = 0;
unsigned long flags;
BUG_ON(cpu_freq != 1200); /* only upgrade 1.2G */
cpu_freq /= 4;
flags = hw_local_irq_save();
val = sprd_greg_read(REG_TYPE_GLOBAL, GR_MPLL_MN);
if ((val & 0x7ff) == cpu_freq)
goto exit;
val = (val & ~0x7ff) | cpu_freq;
sprd_greg_set_bits(REG_TYPE_GLOBAL, BIT(9), GR_GEN1); /* mpll unlock */
sprd_greg_write(REG_TYPE_GLOBAL, val, GR_MPLL_MN);
sprd_greg_clear_bits(REG_TYPE_GLOBAL, BIT(9), GR_GEN1);
exit:
hw_local_irq_restore(flags);
debug("%s 0x%08x\n", __FUNCTION__, val);
return 0;
}
/**
* sdhci_sprd_enable_clock - enable or disable sdio base clock
* @host: sdio host to be set.
* @clock: The clock enable(clock>0) or disable(clock==0).
*
*/
static void sdhci_sprd_enable_clock(struct sdhci_host *host, unsigned int clock)
{
struct sprd_host_data *host_data= sdhci_priv(host);
if(clock == 0){
if (host_data->clk_enable) {
//printk("******* %s, call clk_disable*******\n", mmc_hostname(host->mmc));
clk_disable(host->clk);
host_data->clk_enable = 0;
}
}else{
if (0 == host_data->clk_enable) {
//printk("******* %s, call clk_enable*******\n", mmc_hostname(host->mmc));
clk_enable(host->clk);
host_data->clk_enable = 1;
}
}
pr_debug("clock:%d, host->clock:%d, AHB_CTL0:0x%x\n", clock,host->clock,
sprd_greg_read(REG_TYPE_AHB_GLOBAL, AHB_CTL0));
return;
}
void usb_phy_init(void)
{
#ifdef CONFIG_USB_CORE_IP_293A
/*
* tiger PHY reg is different with previous ,
*7710 has the same core IP with tiger,but PHY reg also diff
*/
sprd_greg_set_bits(REG_TYPE_AHB_GLOBAL,BIT(11), USB_PHY_CTRL);
sprd_greg_set_bits(REG_TYPE_AHB_GLOBAL,BIT(10), USB_PHY_CTRL);
sprd_greg_set_bits(REG_TYPE_AHB_GLOBAL,BIT(20), USB_PHY_CTRL);
sprd_greg_set_bits(REG_TYPE_AHB_GLOBAL,BIT(9), USB_PHY_CTRL);
sprd_greg_clear_bits(REG_TYPE_AHB_GLOBAL,BIT(8), USB_PHY_CTRL);
sprd_greg_set_bits(REG_TYPE_AHB_GLOBAL,BIT(13), USB_PHY_CTRL);
sprd_greg_clear_bits(REG_TYPE_AHB_GLOBAL,BIT(12), USB_PHY_CTRL);
sprd_greg_clear_bits(REG_TYPE_AHB_GLOBAL,BIT(15)|BIT(14), USB_PHY_CTRL);
#else
if (sprd_greg_read(REG_TYPE_AHB_GLOBAL,CHIP_ID) == CHIP_ID_8810S){
/*SMIC chip id == 0x88100001*/
sprd_greg_clear_bits(REG_TYPE_AHB_GLOBAL,BIT(3)|BIT(2), USB_PHY_CTRL);
sprd_greg_set_bits(REG_TYPE_AHB_GLOBAL,BIT(1) | BIT(0), USB_PHY_CTRL);
sprd_greg_set_bits(REG_TYPE_AHB_GLOBAL,BIT(9), USB_PHY_CTRL);
sprd_greg_set_bits(REG_TYPE_AHB_GLOBAL,BIT(16), USB_PHY_CTRL);
sprd_greg_clear_bits(REG_TYPE_AHB_GLOBAL,BIT(17), USB_PHY_CTRL);
sprd_greg_clear_bits(REG_TYPE_AHB_GLOBAL,BIT(13), USB_PHY_CTRL);
sprd_greg_clear_bits(REG_TYPE_AHB_GLOBAL, BIT(12), USB_PHY_CTRL);
sprd_greg_clear_bits(REG_TYPE_AHB_GLOBAL,BIT(15)|BIT(14), USB_PHY_CTRL);
sprd_greg_write(REG_TYPE_AHB_GLOBAL,0x28,USB_SPR_REG);
}else{
/*
* config usb phy controller
*/
sprd_greg_set_bits(REG_TYPE_AHB_GLOBAL,BIT(8), USB_PHY_CTRL);
sprd_greg_set_bits(REG_TYPE_AHB_GLOBAL,BIT(17), USB_PHY_CTRL);
sprd_greg_clear_bits(REG_TYPE_AHB_GLOBAL,BIT(16), USB_PHY_CTRL);
sprd_greg_clear_bits(REG_TYPE_AHB_GLOBAL,BIT(13)|BIT(12), USB_PHY_CTRL);
sprd_greg_set_bits(REG_TYPE_AHB_GLOBAL,BIT(15)|BIT(14), USB_PHY_CTRL);
}
#endif
}
