/**
* mdp5_ctl_commit() - Register Flush
*
* The flush register is used to indicate several registers are all
* programmed, and are safe to update to the back copy of the double
* buffered registers.
*
* Some registers FLUSH bits are shared when the hardware does not have
* dedicated bits for them; handling these is the job of fix_sw_flush().
*
* CTL registers need to be flushed in some circumstances; if that is the
* case, some trigger bits will be present in both flush mask and
* ctl->pending_ctl_trigger.
*
* Return H/W flushed bit mask.
*/
u32 mdp5_ctl_commit(struct mdp5_ctl *ctl, u32 flush_mask)
{
struct mdp5_ctl_manager *ctl_mgr = ctl->ctlm;
struct op_mode *pipeline = &ctl->pipeline;
unsigned long flags;
pipeline->start_mask &= ~flush_mask;
VERB("flush_mask=%x, start_mask=%x, trigger=%x", flush_mask,
pipeline->start_mask, ctl->pending_ctl_trigger);
if (ctl->pending_ctl_trigger & flush_mask) {
flush_mask |= MDP5_CTL_FLUSH_CTL;
ctl->pending_ctl_trigger = 0;
}
flush_mask |= fix_sw_flush(ctl, flush_mask);
flush_mask &= ctl_mgr->flush_hw_mask;
if (flush_mask) {
spin_lock_irqsave(&ctl->hw_lock, flags);
ctl_write(ctl, REG_MDP5_CTL_FLUSH(ctl->id), flush_mask);
spin_unlock_irqrestore(&ctl->hw_lock, flags);
}
if (start_signal_needed(ctl)) {
send_start_signal(ctl);
refill_start_mask(ctl);
}
return flush_mask;
}
/**
* mdp5_ctl_set_encoder_state() - set the encoder state
*
* @enable: true, when encoder is ready for data streaming; false, otherwise.
*
* Note:
* This encoder state is needed to trigger START signal (data path kickoff).
*/
int mdp5_ctl_set_encoder_state(struct mdp5_ctl *ctl, bool enabled)
{
if (WARN_ON(!ctl))
return -EINVAL;
ctl->pipeline.encoder_enabled = enabled;
DBG("intf_%d: %s", ctl->pipeline.intf.num, enabled ? "on" : "off");
if (start_signal_needed(ctl)) {
send_start_signal(ctl);
refill_start_mask(ctl);
}
return 0;
}
/**
* mdp5_ctl_set_encoder_state() - set the encoder state
*
* @enable: true, when encoder is ready for data streaming; false, otherwise.
*
* Note:
* This encoder state is needed to trigger START signal (data path kickoff).
*/
int mdp5_ctl_set_encoder_state(struct mdp5_ctl *ctl,
struct mdp5_pipeline *pipeline,
bool enabled)
{
struct mdp5_interface *intf = pipeline->intf;
if (WARN_ON(!ctl))
return -EINVAL;
ctl->encoder_enabled = enabled;
DBG("intf_%d: %s", intf->num, enabled ? "on" : "off");
if (start_signal_needed(ctl, pipeline)) {
send_start_signal(ctl);
}
return 0;
}
/**
* mdp5_ctl_commit() - Register Flush
*
* The flush register is used to indicate several registers are all
* programmed, and are safe to update to the back copy of the double
* buffered registers.
*
* Some registers FLUSH bits are shared when the hardware does not have
* dedicated bits for them; handling these is the job of fix_sw_flush().
*
* CTL registers need to be flushed in some circumstances; if that is the
* case, some trigger bits will be present in both flush mask and
* ctl->pending_ctl_trigger.
*
* Return H/W flushed bit mask.
*/
u32 mdp5_ctl_commit(struct mdp5_ctl *ctl,
struct mdp5_pipeline *pipeline,
u32 flush_mask, bool start)
{
struct mdp5_ctl_manager *ctl_mgr = ctl->ctlm;
unsigned long flags;
u32 flush_id = ctl->id;
u32 curr_ctl_flush_mask;
VERB("flush_mask=%x, trigger=%x", flush_mask, ctl->pending_ctl_trigger);
if (ctl->pending_ctl_trigger & flush_mask) {
flush_mask |= MDP5_CTL_FLUSH_CTL;
ctl->pending_ctl_trigger = 0;
}
flush_mask |= fix_sw_flush(ctl, pipeline, flush_mask);
flush_mask &= ctl_mgr->flush_hw_mask;
curr_ctl_flush_mask = flush_mask;
fix_for_single_flush(ctl, &flush_mask, &flush_id);
if (!start) {
ctl->flush_mask |= flush_mask;
return curr_ctl_flush_mask;
} else {
flush_mask |= ctl->flush_mask;
ctl->flush_mask = 0;
}
if (flush_mask) {
spin_lock_irqsave(&ctl->hw_lock, flags);
ctl_write(ctl, REG_MDP5_CTL_FLUSH(flush_id), flush_mask);
spin_unlock_irqrestore(&ctl->hw_lock, flags);
}
if (start_signal_needed(ctl, pipeline)) {
send_start_signal(ctl);
}
return curr_ctl_flush_mask;
}
