/*
* Determine i/o configuration for a machine.
*/
void
cpu_configure(void)
{
startrtclock();
#if NBIOS32 > 0
bios32_init();
platform_init();
#endif
x86_64_proc0_tss_ldt_init();
if (config_rootfound("mainbus", NULL) == NULL)
panic("configure: mainbus not configured");
#ifdef INTRDEBUG
intr_printconfig();
#endif
#if NIOAPIC > 0
ioapic_enable();
#endif
#ifdef MULTIPROCESSOR
cpu_init_idle_lwps();
#endif
spl0();
lcr8(0);
}
/*
* void cpu_configure()
*
* Configure all the root devices
* The root devices are expected to configure their own children
*/
void
cpu_configure(void)
{
config_hook_init();
/*
* Configure all the roots.
* We have to have a mainbus
*/
#if 0
startrtclock();
#endif
/*
* Since the ICU is not standard on the ARM we don't know
* if we have one until we find a bridge.
* Since various PCI interrupts could be routed via the ICU
* (for PCI devices in the bridge) we need to set up the ICU
* now so that these interrupts can be established correctly
* i.e. This is a hack.
*/
if (config_rootfound("mainbus", NULL) == NULL)
panic("configure: mainbus not configured");
/* Debugging information */
#ifdef DIAGNOSTIC
dump_spl_masks();
#endif
/* Time to start taking interrupts so lets open the flood gates .... */
(void)spl0();
}
int clock_init(time_t base) {
/* 100 ticks per second */
si->si_rate = 10000;
startrtclock(); /* init the scheduler's clock (not actually part of
the real time clock), and check the BIOS diagnostic
byte that's part of the RTC's nvram */
cpu_initclocks(); /* init the real time clock's periodic interrupt */
inittodr(base); /* read the real time clock's time of day */
return 0;
}
/*
* cpu_configure:
* called at boot time, configure all devices on the system
*/
void
cpu_configure(void)
{
mrg_init(); /* Init Mac ROM Glue */
startrtclock(); /* start before ADB attached */
if (config_rootfound("mainbus", NULL) == NULL)
panic("No mainbus found!");
(void)spl0();
}
/*
* Determine i/o configuration for a machine.
*/
void
configure()
{
startrtclock();
if (config_rootfound("mainbus", NULL) == NULL)
panic("configure: mainbus not configured");
printf("biomask %x netmask %x ttymask %x\n",
(u_short)imask[IPL_BIO], (u_short)imask[IPL_NET],
(u_short)imask[IPL_TTY]);
spl0();
cold = 0;
/* Set up proc0's TSS and LDT (after the FPU is configured). */
i386_proc0_tss_ldt_init();
/* XXX Finish deferred buffer cache allocation. */
i386_bufinit();
}
/*
* Determine i/o configuration for a machine.
*/
void
cpu_configure(void)
{
struct pcb *pcb;
startrtclock();
#if NBIOS32 > 0
bios32_init();
platform_init();
#endif
#ifdef PCIBIOS
pcibios_init();
#endif
if (config_rootfound("mainbus", NULL) == NULL)
panic("configure: mainbus not configured");
#ifdef INTRDEBUG
intr_printconfig();
#endif
#if NIOAPIC > 0
ioapic_enable();
#endif
fpuinit(&cpu_info_primary);
/* resync cr0 after FPU configuration */
pcb = lwp_getpcb(&lwp0);
pcb->pcb_cr0 = rcr0() & ~CR0_TS;
#ifdef MULTIPROCESSOR
/* propagate this to the idle pcb's. */
cpu_init_idle_lwps();
#endif
spl0();
#if NLAPIC > 0
lapic_tpr = 0;
#endif
}