static int add_data_watchpoint(stlink_t *sl, enum watchfun wf, stm32_addr_t addr, unsigned int len)
{
int i = 0;
uint32_t mask;
// computer mask
// find a free watchpoint
// configure
mask = -1;
i = len;
while(i) {
i >>= 1;
mask++;
}
if((mask != -1) && (mask < 16)) {
for(i = 0; i < DATA_WATCH_NUM; i++) {
// is this an empty slot ?
if(data_watches[i].fun == WATCHDISABLED) {
#ifdef DEBUG
printf("insert watchpoint %d addr %x wf %u mask %u len %d\n", i, addr, wf, mask, len);
#endif
data_watches[i].fun = wf;
data_watches[i].addr = addr;
data_watches[i].mask = mask;
// insert comparator address
sl->q_buf[0] = (addr & 0xff);
sl->q_buf[1] = ((addr >> 8) & 0xff);
sl->q_buf[2] = ((addr >> 16) & 0xff);
sl->q_buf[3] = ((addr >> 24) & 0xff);
stlink_write_mem32(sl, 0xE0001020 + i * 16, 4);
// insert mask
memset(sl->q_buf, 0, 4);
sl->q_buf[0] = mask;
stlink_write_mem32(sl, 0xE0001024 + i * 16, 4);
// insert function
memset(sl->q_buf, 0, 4);
sl->q_buf[0] = wf;
stlink_write_mem32(sl, 0xE0001028 + i * 16, 4);
// just to make sure the matched bit is clear !
stlink_read_mem32(sl, 0xE0001028 + i * 16, 4);
return 0;
}
}
}
static void init_data_watchpoints(stlink_t *sl) {
#ifdef DEBUG
printf("init watchpoints\n");
#endif
// set trcena in debug command to turn on dwt unit
stlink_read_mem32(sl, 0xE000EDFC, 4);
sl->q_buf[3] |= 1;
stlink_write_mem32(sl, 0xE000EDFC, 4);
// make sure all watchpoints are cleared
memset(sl->q_buf, 0, 4);
for(int i = 0; i < DATA_WATCH_NUM; i++) {
data_watches[i].fun = WATCHDISABLED;
stlink_write_mem32(sl, 0xe0001028 + i * 16, 4);
}
}
static void
connect_button_cb (GtkWidget *widget, gpointer data)
{
STlinkGUI *gui;
gint i;
gui = STLINK_GUI (data);
if (gui->sl != NULL)
return;
/* try version 1 then version 2 */
gui->sl = stlink_v1_open(0, 1);
if (gui->sl == NULL) {
gui->sl = stlink_open_usb(0, 1);
}
if (gui->sl == NULL) {
stlink_gui_set_info_error_message (gui, "Failed to connect to STLink."); return;
}
/* code below taken from flash/main.c, refactoring might be in order */
if (stlink_current_mode(gui->sl) == STLINK_DEV_DFU_MODE)
stlink_exit_dfu_mode(gui->sl);
if (stlink_current_mode(gui->sl) != STLINK_DEV_DEBUG_MODE)
stlink_enter_swd_mode(gui->sl);
/* Disable DMA - Set All DMA CCR Registers to zero. - AKS 1/7/2013 */
if (gui->sl->chip_id == STM32_CHIPID_F4) {
memset(gui->sl->q_buf, 0, 4);
for (i = 0; i < 8; i++) {
stlink_write_mem32(gui->sl, 0x40026000 + 0x10 + 0x18 * i, 4);
stlink_write_mem32(gui->sl, 0x40026400 + 0x10 + 0x18 * i, 4);
stlink_write_mem32(gui->sl, 0x40026000 + 0x24 + 0x18 * i, 4);
stlink_write_mem32(gui->sl, 0x40026400 + 0x24 + 0x18 * i, 4);
}
}
stlink_gui_set_connected (gui);
}
size_t stlinky_tx(struct stlinky *st, char* buffer, size_t sz)
{
unsigned char rx = 1;
while(rx != 0) {
stlink_read_mem32(st->sl, st->off+4, 4);
rx = (unsigned char) st->sl->q_buf[2];
}
memcpy(st->sl->q_buf, buffer, sz);
size_t rs = sz + (4 - (sz % 4)); /* voodoo */
stlink_write_mem32(st->sl, st->off+8+st->bufsize, rs);
*st->sl->q_buf=(unsigned char) sz;
stlink_write_mem8(st->sl, st->off+6, 1);
return (size_t) rx;
}
int main(int ac, char** av)
{
stlink_t* sl = NULL;
struct opts o;
char serial_buffer[13] = {0};
o.serial = serial_buffer;
int err = -1;
o.size = 0;
if (get_opts(&o, ac - 1, av + 1) == -1)
{
printf("invalid command line\n");
usage();
goto on_error;
}
if (o.devname != NULL) /* stlinkv1 */
{
sl = stlink_v1_open(o.log_level, 1);
if (sl == NULL) goto on_error;
sl->verbose = o.log_level;
}
else /* stlinkv2 */
{
sl = stlink_open_usb(o.log_level, 1, o.serial);
if (sl == NULL) goto on_error;
sl->verbose = o.log_level;
}
if (stlink_current_mode(sl) == STLINK_DEV_DFU_MODE)
stlink_exit_dfu_mode(sl);
if (stlink_current_mode(sl) != STLINK_DEV_DEBUG_MODE)
stlink_enter_swd_mode(sl);
if (o.reset) {
stlink_jtag_reset(sl,2);
stlink_reset(sl);
}
// Disable DMA - Set All DMA CCR Registers to zero. - AKS 1/7/2013
if (sl->chip_id == STM32_CHIPID_F4)
{
memset(sl->q_buf,0,4);
for (int i=0; i<8; i++) {
stlink_write_mem32(sl,0x40026000+0x10+0x18*i,4);
stlink_write_mem32(sl,0x40026400+0x10+0x18*i,4);
stlink_write_mem32(sl,0x40026000+0x24+0x18*i,4);
stlink_write_mem32(sl,0x40026400+0x24+0x18*i,4);
}
}
// Core must be halted to use RAM based flashloaders
stlink_force_debug(sl);
stlink_status(sl);
if (o.cmd == DO_WRITE) /* write */
{
if ((o.addr >= sl->flash_base) &&
(o.addr < sl->flash_base + sl->flash_size)) {
err = stlink_fwrite_flash(sl, o.filename, o.addr);
if (err == -1)
{
printf("stlink_fwrite_flash() == -1\n");
goto on_error;
}
}
else if ((o.addr >= sl->sram_base) &&
(o.addr < sl->sram_base + sl->sram_size)) {
err = stlink_fwrite_sram(sl, o.filename, o.addr);
if (err == -1)
{
printf("stlink_sram_flash() == -1\n");
goto on_error;
}
}
} else if (o.cmd == DO_ERASE)
{
err = stlink_erase_flash_mass(sl);
if (err == -1)
{
printf("stlink_fwrite_flash() == -1\n");
goto on_error;
}
}
else /* read */
{
if ((o.addr >= sl->flash_base) && (o.size == 0) &&
(o.addr < sl->flash_base + sl->flash_size))
o.size = sl->flash_size;
else if ((o.addr >= sl->sram_base) && (o.size == 0) &&
(o.addr < sl->sram_base + sl->sram_size))
o.size = sl->sram_size;
err = stlink_fread(sl, o.filename, o.addr, o.size);
if (err == -1)
{
printf("stlink_fread() == -1\n");
goto on_error;
}
}
if (o.reset) {
stlink_jtag_reset(sl,2);
stlink_reset(sl);
}
/* success */
err = 0;
on_error:
if (sl != NULL)
{
stlink_exit_debug_mode(sl);
stlink_close(sl);
}
return err;
}
int main(int ac, char** av)
{
stlink_t* sl = NULL;
struct flash_opts o;
int err = -1;
uint8_t * mem = NULL;
o.size = 0;
if (flash_get_opts(&o, ac - 1, av + 1) == -1)
{
printf("invalid command line\n");
usage();
return -1;
}
printf("st-flash %s\n", STLINK_VERSION);
if (o.devname != NULL) /* stlinkv1 */
sl = stlink_v1_open(o.log_level, 1);
else /* stlinkv2 */
sl = stlink_open_usb(o.log_level, 1, (char *)o.serial);
if (sl == NULL)
return -1;
if ( o.flash_size != 0u && o.flash_size != sl->flash_size ) {
sl->flash_size = o.flash_size;
printf("Forcing flash size: --flash=0x%08X\n",(unsigned int)sl->flash_size);
}
sl->verbose = o.log_level;
connected_stlink = sl;
signal(SIGINT, &cleanup);
signal(SIGTERM, &cleanup);
signal(SIGSEGV, &cleanup);
if (stlink_current_mode(sl) == STLINK_DEV_DFU_MODE) {
if (stlink_exit_dfu_mode(sl)) {
printf("Failed to exit DFU mode\n");
goto on_error;
}
}
if (stlink_current_mode(sl) != STLINK_DEV_DEBUG_MODE) {
if (stlink_enter_swd_mode(sl)) {
printf("Failed to enter SWD mode\n");
goto on_error;
}
}
if (o.reset){
if (stlink_jtag_reset(sl, 2)) {
printf("Failed to reset JTAG\n");
goto on_error;
}
if (stlink_reset(sl)) {
printf("Failed to reset device\n");
goto on_error;
}
}
// Disable DMA - Set All DMA CCR Registers to zero. - AKS 1/7/2013
if (sl->chip_id == STLINK_CHIPID_STM32_F4)
{
memset(sl->q_buf,0,4);
for (int i=0;i<8;i++) {
stlink_write_mem32(sl,0x40026000+0x10+0x18*i,4);
stlink_write_mem32(sl,0x40026400+0x10+0x18*i,4);
stlink_write_mem32(sl,0x40026000+0x24+0x18*i,4);
stlink_write_mem32(sl,0x40026400+0x24+0x18*i,4);
}
}
// Core must be halted to use RAM based flashloaders
if (stlink_force_debug(sl)) {
printf("Failed to halt the core\n");
goto on_error;
}
if (stlink_status(sl)) {
printf("Failed to get Core's status\n");
goto on_error;
}
if (o.cmd == FLASH_CMD_WRITE) /* write */
{
size_t size = 0;
if(o.format == FLASH_FORMAT_IHEX) {
err = stlink_parse_ihex(o.filename, stlink_get_erased_pattern(sl), &mem, &size, &o.addr);
if (err == -1) {
printf("Cannot parse %s as Intel-HEX file\n", o.filename);
goto on_error;
}
}
if ((o.addr >= sl->flash_base) &&
(o.addr < sl->flash_base + sl->flash_size)) {
if(o.format == FLASH_FORMAT_IHEX)
err = stlink_mwrite_flash(sl, mem, (uint32_t)size, o.addr);
else
err = stlink_fwrite_flash(sl, o.filename, o.addr);
if (err == -1)
{
printf("stlink_fwrite_flash() == -1\n");
goto on_error;
}
}
else if ((o.addr >= sl->sram_base) &&
(o.addr < sl->sram_base + sl->sram_size)) {
if(o.format == FLASH_FORMAT_IHEX)
err = stlink_mwrite_sram(sl, mem, (uint32_t)size, o.addr);
else
err = stlink_fwrite_sram(sl, o.filename, o.addr);
if (err == -1)
{
printf("stlink_fwrite_sram() == -1\n");
goto on_error;
}
}
else {
err = -1;
printf("Unknown memory region\n");
goto on_error;
}
} else if (o.cmd == FLASH_CMD_LOCK)
{
err = stlink_set_read_protection(sl, true);
if(err != 0)
{
printf("stlink_set_read_protection(true) != 0\n");
goto on_error;
}
} else if (o.cmd == FLASH_CMD_UNLOCK)
{
err = stlink_set_read_protection(sl, false);
if(err != 0)
{
printf("stlink_set_read_protection(false) != 0\n");
goto on_error;
}
} else if (o.cmd == FLASH_CMD_ERASE)
{
err = stlink_erase_flash_mass(sl);
if (err == -1)
{
printf("stlink_erase_flash_mass() == -1\n");
goto on_error;
}
} else if (o.cmd == CMD_RESET)
{
if (stlink_jtag_reset(sl, 2)) {
printf("Failed to reset JTAG\n");
goto on_error;
}
if (stlink_reset(sl)) {
printf("Failed to reset device\n");
goto on_error;
}
}
else /* read */
{
if ((o.addr >= sl->flash_base) && (o.size == 0) &&
(o.addr < sl->flash_base + sl->flash_size))
o.size = sl->flash_size;
else if ((o.addr >= sl->sram_base) && (o.size == 0) &&
(o.addr < sl->sram_base + sl->sram_size))
o.size = sl->sram_size;
err = stlink_fread(sl, o.filename, o.format == FLASH_FORMAT_IHEX, o.addr, o.size);
if (err == -1)
{
printf("stlink_fread() == -1\n");
goto on_error;
}
}
if (o.reset){
stlink_jtag_reset(sl,2);
stlink_reset(sl);
}
/* success */
err = 0;
on_error:
stlink_exit_debug_mode(sl);
stlink_close(sl);
free(mem);
return err;
}
int main ( int argc, char *argv[] )
{
stlink_t* sl;
unsigned int ra;
unsigned int rb;
unsigned int flen;
int ret;
if(argc<2)
{
printf(".bin file not specified\n");
return(1);
}
fp=fopen(argv[1],"rb");
if(fp==NULL)
{
printf("Error opening file [%s]\n",argv[1]);
return(1);
}
memset(pdata,0xFF,sizeof(pdata));
flen=fread(pdata,1,sizeof(pdata),fp);
flen+=3;
flen>>=2;
fclose(fp);
sl = stlink_open_usb(10);
if(sl==NULL)
{
printf("stlink_open_usb failed\n");
return(1);
}
printf("-- version\n");
stlink_version(sl);
printf("mode before doing anything: %d\n", stlink_current_mode(sl));
if (stlink_current_mode(sl) == STLINK_DEV_DFU_MODE) {
printf("-- exit_dfu_mode\n");
stlink_exit_dfu_mode(sl);
}
printf("-- enter_swd_mode\n");
stlink_enter_swd_mode(sl);
printf("-- mode after entering swd mode: %d\n", stlink_current_mode(sl));
printf("-- chip id: %#x\n", sl->chip_id);
printf("-- core_id: %#x\n", sl->core_id);
cortex_m3_cpuid_t cpuid;
stlink_cpu_id(sl, &cpuid);
printf("cpuid:impl_id = %0#x, variant = %#x\n", cpuid.implementer_id, cpuid.variant);
printf("cpuid:part = %#x, rev = %#x\n", cpuid.part, cpuid.revision);
// printf("-- status\n");
//stlink_status(sl);
printf("-- reset\n");
stlink_reset(sl);
stlink_force_debug(sl);
// printf("-- status\n");
// stlink_status(sl);
#ifdef LOAD_RAM
printf("-- load\n");
for(ra=0;ra<flen;ra++)
{
write_uint32(sl->q_buf,pdata[ra]);
stlink_write_mem32(sl, 0x20000000+(ra<<2), 4);
}
for(ra=0;ra<8;ra++)
{
stlink_read_mem32(sl, 0x20000000+(ra<<2), 4);
rb=read_uint32(sl->q_buf,0);
printf("[0x%08X] 0x%08X 0x%08X\n",ra,rb,pdata[ra]);
}
printf("-- run\n");
stlink_write_reg(sl, 0x20020000, 13); /* pc register */
stlink_write_reg(sl, 0x20000000, 15); /* pc register */
stlink_run(sl);
ret =0;
#endif //LOAD_RAM
#ifdef LOAD_FLASH
ra=0;
rb=0;
ret=stlink_write_flash(sl,0x08000000,(unsigned char *)pdata,0x4000);
if(ret)
{
printf("stlink_write_flasin error\n");
}
#endif //LOAD_FLASH
printf("-- exit_debug_mode\n");
stlink_exit_debug_mode(sl);
stlink_close(sl);
return 0;
}
int main(int argc, char *argv[]) {
// set scpi lib debug level: 0 for no debug info, 10 for lots
const int scsi_verbose = 2;
char *dev_name;
switch (argc) {
case 1:
fputs(
"\nUsage: stlink-access-test /dev/sg0, sg1, ...\n"
"\n*** Notice: The stlink firmware violates the USB standard.\n"
"*** If you plug-in the discovery's stlink, wait a several\n"
"*** minutes to let the kernel driver swallow the broken device.\n"
"*** Watch:\ntail -f /var/log/messages\n"
"*** This command sequence can shorten the waiting time and fix some issues.\n"
"*** Unplug the stlink and execute once as root:\n"
"modprobe -r usb-storage && modprobe usb-storage quirks=483:3744:lrwsro\n\n",
stderr);
return EXIT_FAILURE;
case 2:
dev_name = argv[1];
break;
default:
return EXIT_FAILURE;
}
fputs("*** stlink access test ***\n", stderr);
fprintf(stderr, "Using sg_lib %s : scsi_pt %s\n", sg_lib_version(),
scsi_pt_version());
stlink_t *sl = stlink_quirk_open(dev_name, scsi_verbose);
if (sl == NULL)
return EXIT_FAILURE;
// we are in mass mode, go to swd
stlink_enter_swd_mode(sl);
stlink_current_mode(sl);
stlink_core_id(sl);
//----------------------------------------------------------------------
stlink_status(sl);
//stlink_force_debug(sl);
stlink_reset(sl);
stlink_status(sl);
#if 0
// core system control block
stlink_read_mem32(sl, 0xe000ed00, 4);
DD(sl, "cpu id base register: SCB_CPUID = got 0x%08x expect 0x411fc231", read_uint32(sl->q_buf, 0));
// no MPU
stlink_read_mem32(sl, 0xe000ed90, 4);
DD(sl, "mpu type register: MPU_TYPER = got 0x%08x expect 0x0", read_uint32(sl->q_buf, 0));
stlink_read_mem32(sl, 0xe000edf0, 4);
DD(sl, "DHCSR = 0x%08x", read_uint32(sl->q_buf, 0));
stlink_read_mem32(sl, 0x4001100c, 4);
DD(sl, "GPIOC_ODR = 0x%08x", read_uint32(sl->q_buf, 0));
#endif
#if 0
// happy new year 2011: let blink all the leds
// see "RM0041 Reference manual - STM32F100xx advanced ARM-based 32-bit MCUs"
#define GPIOC 0x40011000 // port C
#define GPIOC_CRH (GPIOC + 0x04) // port configuration register high
#define GPIOC_ODR (GPIOC + 0x0c) // port output data register
#define LED_BLUE (1<<8) // pin 8
#define LED_GREEN (1<<9) // pin 9
stlink_read_mem32(sl, GPIOC_CRH, 4);
uint32_t io_conf = read_uint32(sl->q_buf, 0);
DD(sl, "GPIOC_CRH = 0x%08x", io_conf);
// set: general purpose output push-pull, output mode, max speed 10 MHz.
write_uint32(sl->q_buf, 0x44444411);
stlink_write_mem32(sl, GPIOC_CRH, 4);
clear_buf(sl);
for (int i = 0; i < 100; i++) {
write_uint32(sl->q_buf, LED_BLUE | LED_GREEN);
stlink_write_mem32(sl, GPIOC_ODR, 4);
/* stlink_read_mem32(sl, 0x4001100c, 4); */
/* DD(sl, "GPIOC_ODR = 0x%08x", read_uint32(sl->q_buf, 0)); */
delay(100);
clear_buf(sl);
stlink_write_mem32(sl, GPIOC_ODR, 4); // PC lo
delay(100);
}
write_uint32(sl->q_buf, io_conf); // set old state
#endif
#if 0
// TODO rtfm: stlink doesn't have flash write routines
// writing to the flash area confuses the fw for the next read access
//stlink_read_mem32(sl, 0, 1024*6);
// flash 0x08000000 128kB
fputs("++++++++++ read a flash at 0x0800 0000\n", stderr);
stlink_read_mem32(sl, 0x08000000, 1024 * 6); //max 6kB
clear_buf(sl);
stlink_read_mem32(sl, 0x08000c00, 5);
stlink_read_mem32(sl, 0x08000c00, 4);
mark_buf(sl);
stlink_write_mem32(sl, 0x08000c00, 4);
stlink_read_mem32(sl, 0x08000c00, 256);
stlink_read_mem32(sl, 0x08000c00, 256);
#endif
#if 0
// sram 0x20000000 8kB
fputs("\n++++++++++ read/write 8bit, sram at 0x2000 0000 ++++++++++++++++\n\n", stderr);
clear_buf(sl);
stlink_write_mem8(sl, 0x20000000, 16);
mark_buf(sl);
stlink_write_mem8(sl, 0x20000000, 1);
stlink_write_mem8(sl, 0x20000001, 1);
stlink_write_mem8(sl, 0x2000000b, 3);
stlink_read_mem32(sl, 0x20000000, 16);
#endif
#if 0
// a not aligned mem32 access doesn't work indeed
fputs("\n++++++++++ read/write 32bit, sram at 0x2000 0000 ++++++++++++++++\n\n", stderr);
clear_buf(sl);
stlink_write_mem8(sl, 0x20000000, 32);
mark_buf(sl);
stlink_write_mem32(sl, 0x20000000, 1);
stlink_read_mem32(sl, 0x20000000, 16);
mark_buf(sl);
stlink_write_mem32(sl, 0x20000001, 1);
stlink_read_mem32(sl, 0x20000000, 16);
mark_buf(sl);
stlink_write_mem32(sl, 0x2000000b, 3);
stlink_read_mem32(sl, 0x20000000, 16);
mark_buf(sl);
stlink_write_mem32(sl, 0x20000000, 17);
stlink_read_mem32(sl, 0x20000000, 32);
#endif
#if 0
// sram 0x20000000 8kB
fputs("++++++++++ read/write 32bit, sram at 0x2000 0000 ++++++++++++\n", stderr);
mark_buf(sl);
stlink_write_mem8(sl, 0x20000000, 64);
stlink_read_mem32(sl, 0x20000000, 64);
mark_buf(sl);
stlink_write_mem32(sl, 0x20000000, 1024 * 8); //8kB
stlink_read_mem32(sl, 0x20000000, 1024 * 6);
stlink_read_mem32(sl, 0x20000000 + 1024 * 6, 1024 * 2);
#endif
#if 0
stlink_read_all_regs(sl);
stlink_step(sl);
fputs("++++++++++ write r0 = 0x12345678\n", stderr);
stlink_write_reg(sl, 0x12345678, 0);
stlink_read_reg(sl, 0);
stlink_read_all_regs(sl);
#endif
#if 0
stlink_run(sl);
stlink_status(sl);
stlink_force_debug(sl);
stlink_status(sl);
#endif
#if 1 /* read the system bootloader */
fputs("\n++++++++++ reading bootloader ++++++++++++++++\n\n", stderr);
stlink_fread(sl, "/tmp/barfoo", sl->sys_base, sl->sys_size);
#endif
#if 0 /* read the flash memory */
fputs("\n+++++++ read flash memory\n\n", stderr);
/* mark_buf(sl); */
stlink_read_mem32(sl, 0x08000000, 4);
#endif
#if 0 /* flash programming */
fputs("\n+++++++ program flash memory\n\n", stderr);
stlink_fwrite_flash(sl, "/tmp/foobar", 0x08000000);
#endif
#if 0 /* check file contents */
fputs("\n+++++++ check flash memory\n\n", stderr);
{
const int res = stlink_fcheck_flash(sl, "/tmp/foobar", 0x08000000);
printf("_____ stlink_fcheck_flash() == %d\n", res);
}
#endif
#if 0
fputs("\n+++++++ sram write and execute\n\n", stderr);
stlink_fwrite_sram(sl, "/tmp/foobar", sl->sram_base);
stlink_run_at(sl, sl->sram_base);
#endif
stlink_run(sl);
stlink_status(sl);
//----------------------------------------------------------------------
// back to mass mode, just in case ...
stlink_exit_debug_mode(sl);
stlink_current_mode(sl);
stlink_close(sl);
//fflush(stderr); fflush(stdout);
return EXIT_SUCCESS;
}
int main(int argc, char *argv[]) {
/* Avoid unused parameter warning */
(void)argv;
// set scpi lib debug level: 0 for no debug info, 10 for lots
switch (argc) {
case 1:
fputs(
"\nUsage: stlink-access-test [anything at all] ...\n"
"\n*** Notice: The stlink firmware violates the USB standard.\n"
"*** Because we just use libusb, we can just tell the kernel's\n"
"*** driver to simply ignore the device...\n"
"*** Unplug the stlink and execute once as root:\n"
"modprobe -r usb-storage && modprobe usb-storage quirks=483:3744:i\n\n",
stderr);
return EXIT_FAILURE;
default:
break;
}
stlink_t *sl = stlink_v1_open(99, 1);
if (sl == NULL)
return EXIT_FAILURE;
// we are in mass mode, go to swd
stlink_enter_swd_mode(sl);
stlink_current_mode(sl);
stlink_core_id(sl);
//----------------------------------------------------------------------
stlink_status(sl);
//stlink_force_debug(sl);
stlink_reset(sl);
stlink_status(sl);
// core system control block
stlink_read_mem32(sl, 0xe000ed00, 4);
DLOG("cpu id base register: SCB_CPUID = got 0x%08x expect 0x411fc231\n", read_uint32(sl->q_buf, 0));
// no MPU
stlink_read_mem32(sl, 0xe000ed90, 4);
DLOG("mpu type register: MPU_TYPER = got 0x%08x expect 0x0\n", read_uint32(sl->q_buf, 0));
#if 0
stlink_read_mem32(sl, 0xe000edf0, 4);
DD(sl, "DHCSR = 0x%08x", read_uint32(sl->q_buf, 0));
stlink_read_mem32(sl, 0x4001100c, 4);
DD(sl, "GPIOC_ODR = 0x%08x", read_uint32(sl->q_buf, 0));
#endif
#if 0
// happy new year 2011: let blink all the leds
// see "RM0041 Reference manual - STM32F100xx advanced ARM-based 32-bit MCUs"
#define GPIOC 0x40011000 // port C
#define GPIOC_CRH (GPIOC + 0x04) // port configuration register high
#define GPIOC_ODR (GPIOC + 0x0c) // port output data register
#define LED_BLUE (1<<8) // pin 8
#define LED_GREEN (1<<9) // pin 9
stlink_read_mem32(sl, GPIOC_CRH, 4);
uint32_t io_conf = read_uint32(sl->q_buf, 0);
DLOG("GPIOC_CRH = 0x%08x\n", io_conf);
// set: general purpose output push-pull, output mode, max speed 10 MHz.
write_uint32(sl->q_buf, 0x44444411);
stlink_write_mem32(sl, GPIOC_CRH, 4);
memset(sl->q_buf, 0, sizeof(sl->q_buf));
for (int i = 0; i < 100; i++) {
write_uint32(sl->q_buf, LED_BLUE | LED_GREEN);
stlink_write_mem32(sl, GPIOC_ODR, 4);
/* stlink_read_mem32(sl, 0x4001100c, 4); */
/* DD(sl, "GPIOC_ODR = 0x%08x", read_uint32(sl->q_buf, 0)); */
usleep(100 * 1000);
memset(sl->q_buf, 0, sizeof(sl->q_buf));
stlink_write_mem32(sl, GPIOC_ODR, 4); // PC lo
usleep(100 * 1000);
}
write_uint32(sl->q_buf, io_conf); // set old state
#endif
#if 0
// TODO rtfm: stlink doesn't have flash write routines
// writing to the flash area confuses the fw for the next read access
//stlink_read_mem32(sl, 0, 1024*6);
// flash 0x08000000 128kB
fputs("++++++++++ read a flash at 0x0800 0000\n", stderr);
stlink_read_mem32(sl, 0x08000000, 1024 * 6); //max 6kB
clear_buf(sl);
stlink_read_mem32(sl, 0x08000c00, 5);
stlink_read_mem32(sl, 0x08000c00, 4);
mark_buf(sl);
stlink_write_mem32(sl, 0x08000c00, 4);
stlink_read_mem32(sl, 0x08000c00, 256);
stlink_read_mem32(sl, 0x08000c00, 256);
#endif
#if 0
// sram 0x20000000 8kB
fputs("\n++++++++++ read/write 8bit, sram at 0x2000 0000 ++++++++++++++++\n\n", stderr);
memset(sl->q_buf, 0, sizeof(sl->q_buf));
mark_buf(sl);
//stlink_write_mem8(sl, 0x20000000, 16);
//stlink_write_mem8(sl, 0x20000000, 1);
//stlink_write_mem8(sl, 0x20000001, 1);
stlink_write_mem8(sl, 0x2000000b, 3);
stlink_read_mem32(sl, 0x20000000, 16);
#endif
#if 0
// a not aligned mem32 access doesn't work indeed
fputs("\n++++++++++ read/write 32bit, sram at 0x2000 0000 ++++++++++++++++\n\n", stderr);
memset(sl->q_buf, 0, sizeof(sl->q_buf));
mark_buf(sl);
stlink_write_mem32(sl, 0x20000000, 1);
stlink_read_mem32(sl, 0x20000000, 16);
mark_buf(sl);
stlink_write_mem32(sl, 0x20000001, 1);
stlink_read_mem32(sl, 0x20000000, 16);
mark_buf(sl);
stlink_write_mem32(sl, 0x2000000b, 3);
stlink_read_mem32(sl, 0x20000000, 16);
mark_buf(sl);
stlink_write_mem32(sl, 0x20000000, 17);
stlink_read_mem32(sl, 0x20000000, 32);
#endif
#if 0
// sram 0x20000000 8kB
fputs("++++++++++ read/write 32bit, sram at 0x2000 0000 ++++++++++++\n", stderr);
memset(sl->q_buf, 0, sizeof(sl->q_buf));
mark_buf(sl);
stlink_write_mem8(sl, 0x20000000, 64);
stlink_read_mem32(sl, 0x20000000, 64);
mark_buf(sl);
stlink_write_mem32(sl, 0x20000000, 1024 * 8); //8kB
stlink_read_mem32(sl, 0x20000000, 1024 * 6);
stlink_read_mem32(sl, 0x20000000 + 1024 * 6, 1024 * 2);
#endif
#if 1
reg regs;
stlink_read_all_regs(sl, ®s);
stlink_step(sl);
fputs("++++++++++ write r0 = 0x12345678\n", stderr);
stlink_write_reg(sl, 0x12345678, 0);
stlink_read_reg(sl, 0, ®s);
stlink_read_all_regs(sl, ®s);
#endif
#if 0
stlink_run(sl);
stlink_status(sl);
stlink_force_debug(sl);
stlink_status(sl);
#endif
#if 0 /* read the system bootloader */
fputs("\n++++++++++ reading bootloader ++++++++++++++++\n\n", stderr);
stlink_fread(sl, "/tmp/barfoo", sl->sys_base, sl->sys_size);
#endif
#if 0 /* read the flash memory */
fputs("\n+++++++ read flash memory\n\n", stderr);
/* mark_buf(sl); */
stlink_read_mem32(sl, 0x08000000, 4);
#endif
#if 0 /* flash programming */
fputs("\n+++++++ program flash memory\n\n", stderr);
stlink_fwrite_flash(sl, "/tmp/foobar", 0x08000000);
#endif
#if 0 /* check file contents */
fputs("\n+++++++ check flash memory\n\n", stderr);
{
const int res = stlink_fcheck_flash(sl, "/tmp/foobar", 0x08000000);
printf("_____ stlink_fcheck_flash() == %d\n", res);
}
#endif
#if 0
fputs("\n+++++++ sram write and execute\n\n", stderr);
stlink_fwrite_sram(sl, "/tmp/foobar", sl->sram_base);
stlink_run_at(sl, sl->sram_base);
#endif
#if 0
stlink_run(sl);
stlink_status(sl);
//----------------------------------------------------------------------
// back to mass mode, just in case ...
stlink_exit_debug_mode(sl);
stlink_current_mode(sl);
stlink_close(sl);
#endif
//fflush(stderr); fflush(stdout);
return EXIT_SUCCESS;
}
int main(int ac, char** av)
{
(void)ac;
(void)av;
stlink_t* sl;
reg regs;
sl = stlink_open_usb(10, 1, NULL);
if (sl != NULL) {
printf("-- version\n");
stlink_version(sl);
printf("mode before doing anything: %d\n", stlink_current_mode(sl));
if (stlink_current_mode(sl) == STLINK_DEV_DFU_MODE) {
printf("-- exit_dfu_mode\n");
stlink_exit_dfu_mode(sl);
}
printf("-- enter_swd_mode\n");
stlink_enter_swd_mode(sl);
printf("-- mode after entering swd mode: %d\n", stlink_current_mode(sl));
printf("-- chip id: %#x\n", sl->chip_id);
printf("-- core_id: %#x\n", sl->core_id);
cortex_m3_cpuid_t cpuid;
stlink_cpu_id(sl, &cpuid);
printf("cpuid:impl_id = %0#x, variant = %#x\n", cpuid.implementer_id, cpuid.variant);
printf("cpuid:part = %#x, rev = %#x\n", cpuid.part, cpuid.revision);
printf("-- read_sram\n");
static const uint32_t sram_base = STM32_SRAM_BASE;
uint32_t off;
for (off = 0; off < 16; off += 4)
stlink_read_mem32(sl, sram_base + off, 4);
printf("FP_CTRL\n");
stlink_read_mem32(sl, STLINK_REG_CM3_FP_CTRL, 4);
// no idea what reg this is.. */
// stlink_read_mem32(sl, 0xe000ed90, 4);
// no idea what register this is...
// stlink_read_mem32(sl, 0xe000edf0, 4);
// offset 0xC into TIM11 register? TIMx_DIER?
// stlink_read_mem32(sl, 0x4001100c, 4); */
/* Test 32 bit Write */
write_uint32(sl->q_buf,0x01234567);
stlink_write_mem32(sl,0x200000a8,4);
write_uint32(sl->q_buf,0x89abcdef);
stlink_write_mem32(sl,0x200000ac, 4);
stlink_read_mem32(sl, 0x200000a8, 4);
stlink_read_mem32(sl, 0x200000ac, 4);
/* Test 8 bit write */
write_uint32(sl->q_buf,0x01234567);
stlink_write_mem8(sl,0x200001a8,3);
write_uint32(sl->q_buf,0x89abcdef);
stlink_write_mem8(sl, 0x200001ac, 3);
stlink_read_mem32(sl, 0x200001a8, 4);
stlink_read_mem32(sl, 0x200001ac, 4);
printf("-- status\n");
stlink_status(sl);
printf("-- reset\n");
stlink_reset(sl);
stlink_force_debug(sl);
/* Test reg write*/
stlink_write_reg(sl, 0x01234567, 3);
stlink_write_reg(sl, 0x89abcdef, 4);
stlink_write_reg(sl, 0x12345678, 15);
for (off = 0; off < 21; off += 1)
stlink_read_reg(sl, off, ®s);
stlink_read_all_regs(sl, ®s);
printf("-- status\n");
stlink_status(sl);
printf("-- step\n");
stlink_step(sl);
printf("-- run\n");
stlink_run(sl);
printf("-- exit_debug_mode\n");
stlink_exit_debug_mode(sl);
stlink_close(sl);
}
return 0;
}
int stlink_flash_loader_write_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* size)
{
const uint8_t* loader_code;
size_t loader_size;
if (sl->chip_id == STLINK_CHIPID_STM32_L1_MEDIUM || sl->chip_id == STLINK_CHIPID_STM32_L1_CAT2
|| sl->chip_id == STLINK_CHIPID_STM32_L1_MEDIUM_PLUS || sl->chip_id == STLINK_CHIPID_STM32_L1_HIGH
|| sl->chip_id == STLINK_CHIPID_STM32_L152_RE
|| sl->chip_id == STLINK_CHIPID_STM32_L0 || sl->chip_id == STLINK_CHIPID_STM32_L0_CAT5 || sl->chip_id == STLINK_CHIPID_STM32_L0_CAT2) { /* stm32l */
loader_code = loader_code_stm32l;
loader_size = sizeof(loader_code_stm32l);
} else if (sl->core_id == STM32VL_CORE_ID
|| sl->chip_id == STLINK_CHIPID_STM32_F3
|| sl->chip_id == STLINK_CHIPID_STM32_F3_SMALL
|| sl->chip_id == STLINK_CHIPID_STM32_F303_HIGH
|| sl->chip_id == STLINK_CHIPID_STM32_F37x
|| sl->chip_id == STLINK_CHIPID_STM32_F334) {
loader_code = loader_code_stm32vl;
loader_size = sizeof(loader_code_stm32vl);
} else if (sl->chip_id == STLINK_CHIPID_STM32_F2 ||
sl->chip_id == STLINK_CHIPID_STM32_F4 ||
sl->chip_id == STLINK_CHIPID_STM32_F4_DE ||
sl->chip_id == STLINK_CHIPID_STM32_F4_LP ||
sl->chip_id == STLINK_CHIPID_STM32_F4_HD ||
sl->chip_id == STLINK_CHIPID_STM32_F4_DSI ||
sl->chip_id == STLINK_CHIPID_STM32_F410 ||
sl->chip_id == STLINK_CHIPID_STM32_F411RE ||
sl->chip_id == STLINK_CHIPID_STM32_F446
) {
if( sl->version.stlink_v == 1 ) {
printf("STLINK V1 cannot read voltage, defaulting to 32-bit writes on F4 devices\n");
loader_code = loader_code_stm32f4;
loader_size = sizeof(loader_code_stm32f4);
}
else {
int voltage = stlink_target_voltage(sl);
if (voltage == -1) {
printf("Failed to read Target voltage\n");
return voltage;
} else if (voltage > 2700) {
loader_code = loader_code_stm32f4;
loader_size = sizeof(loader_code_stm32f4);
} else {
loader_code = loader_code_stm32f4_lv;
loader_size = sizeof(loader_code_stm32f4_lv);
}
}
} else if (sl->core_id == STM32F7_CORE_ID ||
sl->chip_id == STLINK_CHIPID_STM32_F7 ||
sl->chip_id == STLINK_CHIPID_STM32_F7XXXX) {
loader_code = loader_code_stm32f7;
loader_size = sizeof(loader_code_stm32f7);
} else if (sl->chip_id == STLINK_CHIPID_STM32_F0 || sl->chip_id == STLINK_CHIPID_STM32_F04 || sl->chip_id == STLINK_CHIPID_STM32_F0_CAN || sl->chip_id == STLINK_CHIPID_STM32_F0_SMALL || sl->chip_id == STLINK_CHIPID_STM32_F09X) {
loader_code = loader_code_stm32f0;
loader_size = sizeof(loader_code_stm32f0);
} else if (sl->chip_id == STLINK_CHIPID_STM32_L4) {
loader_code = loader_code_stm32l4;
loader_size = sizeof(loader_code_stm32l4);
} else {
ELOG("unknown coreid, not sure what flash loader to use, aborting! coreid: %x, chipid: %x\n", sl->core_id, sl->chip_id);
return -1;
}
memcpy(sl->q_buf, loader_code, loader_size);
stlink_write_mem32(sl, sl->sram_base, loader_size);
*addr = sl->sram_base;
*size = loader_size;
/* success */
return 0;
}
