void queue_plug(struct lba_data *data) { u32 ctrl1; clk_enable(data->clk); if (clk <= 0) clk = 24000; /* safe setting, some chips do not work on speeds >= 24kHz */ clk_set_rate(data->clk, clk); clk = clk_get_rate(data->clk); stmp3xxx_reset_block(HW_GPMI_CTRL0 + REGS_GPMI_BASE, 1); ctrl1 = __raw_readl(REGS_GPMI_BASE + HW_GPMI_CTRL1); /* write protection OFF */ ctrl1 |= BM_GPMI_CTRL1_DEV_RESET; /* IRQ polarity */ ctrl1 |= BM_GPMI_CTRL1_ATA_IRQRDY_POLARITY; /* ...and ECC module */ /*HW_GPMI_CTRL1_SET(bch_mode());*/ /* choose NAND mode (1 means ATA, 0 - NAND */ ctrl1 &= ~BM_GPMI_CTRL1_GPMI_MODE; __raw_writel(ctrl1, REGS_GPMI_BASE + HW_GPMI_CTRL1); gpmi_set_timings(data, &gpmi_safe_timing); }
static int stmp_appuart_startup(struct uart_port *u) { struct stmp_appuart_port *s = to_appuart(u); int err; dev_dbg(s->dev, "%s\n", __func__); s->tx_buffer_index = 0; err = stmp_appuart_request_irqs(s); if (err) goto out; if (!s->keep_irq) /* Release the block from reset and start the clocks. */ stmp3xxx_reset_block(s->mem, 0); HW_UARTAPP_CTRL2_SET_NB(s->mem, BM_UARTAPP_CTRL2_UARTEN); /* Enable the Application UART DMA bits. */ if (!pio_mode) { HW_UARTAPP_CTRL2_SET_NB(s->mem, BM_UARTAPP_CTRL2_TXDMAE | BM_UARTAPP_CTRL2_RXDMAE | BM_UARTAPP_CTRL2_DMAONERR); /* clear any pending interrupts */ HW_UARTAPP_INTR_WR_NB(s->mem, 0); /* reset all dma channels */ stmp3xxx_dma_reset_channel(s->dma_tx); stmp3xxx_dma_reset_channel(s->dma_rx); } else { HW_UARTAPP_INTR_WR_NB(s->mem, BM_UARTAPP_INTR_RXIEN | BM_UARTAPP_INTR_RTIEN); } HW_UARTAPP_INTR_SET_NB(s->mem, BM_UARTAPP_INTR_CTSMIEN); /* * Enable fifo so all four bytes of a DMA word are written to * output (otherwise, only the LSB is written, ie. 1 in 4 bytes) */ HW_UARTAPP_LINECTRL_SET_NB(s->mem, BM_UARTAPP_LINECTRL_FEN); if (!pio_mode) { #ifndef RX_CHAIN stmp_appuart_submit_rx(s); #else circ_clear_chain(&s->rx_chain); stmp3xxx_dma_go(s->dma_rx, &s->rxd[0], 0); circ_advance_active(&s->rx_chain, 1); #endif } else { init_timer(&timer_task); timer_task.function = stmp_appuart_check_rx; timer_task.expires = jiffies + HZ; timer_task.data = (unsigned long)s; add_timer(&timer_task); } out: return err; }
/* Reset ssp peripheral to default values */ static void stmp3xxx_mmc_reset(struct stmp3xxx_mmc_host *host) { u32 ssp_ctrl0; u32 ssp_ctrl1; stmp3xxx_reset_block(host->ssp_base, 0); /* Configure SSP Control Register 0 */ ssp_ctrl0 = BM_SSP_CTRL0_IGNORE_CRC | BF(BV_SSP_CTRL0_BUS_WIDTH__ONE_BIT, SSP_CTRL0_BUS_WIDTH); /* Configure SSP Control Register 1 */ ssp_ctrl1 = BM_SSP_CTRL1_DMA_ENABLE | BM_SSP_CTRL1_POLARITY | BM_SSP_CTRL1_RECV_TIMEOUT_IRQ_EN | BM_SSP_CTRL1_DATA_CRC_IRQ_EN | BM_SSP_CTRL1_DATA_TIMEOUT_IRQ_EN | BM_SSP_CTRL1_RESP_TIMEOUT_IRQ_EN | BM_SSP_CTRL1_RESP_ERR_IRQ_EN | BF(BV_SSP_CTRL1_WORD_LENGTH__EIGHT_BITS, SSP_CTRL1_WORD_LENGTH) | BF(BV_SSP_CTRL1_SSP_MODE__SD_MMC, SSP_CTRL1_SSP_MODE); __raw_writel(BF(0xFFFF, SSP_TIMING_TIMEOUT) | BF(2, SSP_TIMING_CLOCK_DIVIDE) | BF(0, SSP_TIMING_CLOCK_RATE), host->ssp_base + HW_SSP_TIMING); /* Write the SSP Control Register 0 and 1 values out to the interface */ __raw_writel(ssp_ctrl0, host->ssp_base + HW_SSP_CTRL0); __raw_writel(ssp_ctrl1, host->ssp_base + HW_SSP_CTRL1); }
static int init_bl(struct stmp3xxx_platform_bl_data *data) { int ret = 0; pwm_clk = clk_get(NULL, "pwm"); if (IS_ERR(pwm_clk)) { ret = PTR_ERR(pwm_clk); goto out; } clk_enable(pwm_clk); stmp3xxx_reset_block(REGS_PWM_BASE, 1); ret = stmp3xxx_request_pin(PINID_PWM2, PIN_FUN1, "lcd_hx8238a"); if (ret) goto out_mux; stmp3xxx_pin_voltage(PINID_PWM2, PIN_12MA, "lcd_hx8238a"); stmp3xxx_pin_strength(PINID_PWM2, PIN_3_3V, "lcd_hx8238a"); stmp3xxx_clearl(BM_PWM_CTRL_PWM2_ENABLE, REGS_PWM_BASE + HW_PWM_CTRL); stmp3xxx_setl(BM_PWM_CTRL_PWM2_ANA_CTRL_ENABLE, REGS_PWM_BASE + HW_PWM_CTRL); __raw_writel(BF(10, PWM_ACTIVEn_INACTIVE) | BF(5, PWM_ACTIVEn_ACTIVE), REGS_PWM_BASE + HW_PWM_ACTIVEn(2)); __raw_writel(BF(1, PWM_PERIODn_CDIV) | /* divide by 2 */ BF(2, PWM_PERIODn_INACTIVE_STATE) | /* low */ BF(3, PWM_PERIODn_ACTIVE_STATE) | /* high */ BF(14, PWM_PERIODn_PERIOD), REGS_PWM_BASE + HW_PWM_PERIODn(2)); return 0; out_mux: clk_put(pwm_clk); out: return ret; }
static int init_bl(struct stmp3xxx_platform_bl_data *data) { int ret = 0; pwm_clk = clk_get(NULL, "pwm"); if (IS_ERR(pwm_clk)) { ret = PTR_ERR(pwm_clk); goto out; } clk_enable(pwm_clk); stmp3xxx_reset_block(REGS_PWM_BASE, 1); ret = stmp3xxx_request_pin(PINID_PWM2, PIN_FUN1, "lcd_lms430"); if (ret) goto out_mux; stmp3xxx_pin_voltage(PINID_PWM2, PIN_8MA, "lcd_lms430"); stmp3xxx_pin_strength(PINID_PWM2, PIN_3_3V, "lcd_lms430"); HW_PWM_ACTIVEn_WR(2, BF_PWM_ACTIVEn_INACTIVE(0) | BF_PWM_ACTIVEn_ACTIVE(0)); HW_PWM_PERIODn_WR(2, BF_PWM_PERIODn_CDIV(6) | /* divide by 64 */ BF_PWM_PERIODn_INACTIVE_STATE(2) | /* low */ BF_PWM_PERIODn_ACTIVE_STATE(3) | /* high */ BF_PWM_PERIODn_PERIOD(599)); HW_PWM_CTRL_SET(BM_PWM_CTRL_PWM2_ENABLE); return 0; out_mux: clk_put(pwm_clk); out: return ret; }
static void __init stmp3xxx_init_timer(void) { cksrc_stmp3xxx.mult = clocksource_hz2mult(CLOCK_TICK_RATE, cksrc_stmp3xxx.shift); ckevt_timrot.mult = div_sc(CLOCK_TICK_RATE, NSEC_PER_SEC, ckevt_timrot.shift); ckevt_timrot.min_delta_ns = clockevent_delta2ns(2, &ckevt_timrot); ckevt_timrot.max_delta_ns = clockevent_delta2ns(0xFFF, &ckevt_timrot); ckevt_timrot.cpumask = cpumask_of(0); stmp3xxx_reset_block(REGS_TIMROT_BASE, false); /* clear two timers */ __raw_writel(0, REGS_TIMROT_BASE + HW_TIMROT_TIMCOUNT0); __raw_writel(0, REGS_TIMROT_BASE + HW_TIMROT_TIMCOUNT1); /* configure them */ __raw_writel( (8 << BP_TIMROT_TIMCTRLn_SELECT) | /* 32 kHz */ BM_TIMROT_TIMCTRLn_RELOAD | BM_TIMROT_TIMCTRLn_UPDATE | BM_TIMROT_TIMCTRLn_IRQ_EN, REGS_TIMROT_BASE + HW_TIMROT_TIMCTRL0); __raw_writel( (8 << BP_TIMROT_TIMCTRLn_SELECT) | /* 32 kHz */ BM_TIMROT_TIMCTRLn_RELOAD | BM_TIMROT_TIMCTRLn_UPDATE | BM_TIMROT_TIMCTRLn_IRQ_EN, REGS_TIMROT_BASE + HW_TIMROT_TIMCTRL1); __raw_writel(CLOCK_TICK_RATE / HZ - 1, REGS_TIMROT_BASE + HW_TIMROT_TIMCOUNT0); __raw_writel(0xFFFF, REGS_TIMROT_BASE + HW_TIMROT_TIMCOUNT1); setup_irq(IRQ_TIMER0, &stmp3xxx_timer_irq); clocksource_register(&cksrc_stmp3xxx); clockevents_register_device(&ckevt_timrot); }