__s32 BSP_disp_restore_image_reg(__u32 sel, __u32 addr)
{
__u32 i = 0;
__u32 value = 0;
__u32 reg_base = 0;
if(sel == 0)
{
reg_base = gdisp.init_para.base_image0;
}
else
{
reg_base = gdisp.init_para.base_image1;
}
DE_BE_Reg_Init(sel);
for(i=4; i<0xe00 - 0x800; i+=4)
{
value = sys_get_wvalue(addr + i);
sys_put_wvalue(reg_base + 0x800 + i,value);
}
value = sys_get_wvalue(addr);
sys_put_wvalue(reg_base + 0x800,value);
return 0;
}
__s32 bsp_disp_restore_image_reg(__u32 screen_id, __u32 addr)
{
__u32 i = 0;
__u32 value = 0;
__u32 reg_base = 0;
if(addr == 0) {
DE_WRN("bsp_disp_restore_image_reg, addr is NULL!");
return -1;
}
if(screen_id == 0) {
reg_base = gdisp.init_para.reg_base[DISP_MOD_BE0];
} else {
reg_base = gdisp.init_para.reg_base[DISP_MOD_BE1];
}
DE_BE_Reg_Init(screen_id);
for(i=4; i<0xe00 - 0x800; i+=4) {
value = sys_get_wvalue(addr + i);
sys_put_wvalue(reg_base + 0x800 + i,value);
}
value = sys_get_wvalue(addr);
sys_put_wvalue(reg_base + 0x800,value);
return 0;
}
__s32 bsp_disp_restore_scaler_reg(__u32 scaler_index, __u32 addr)
{
__u32 i = 0;
__u32 value = 0;
__u32 reg_base = 0;
if(scaler_index == 0) {
reg_base = gdisp.init_para.reg_base[DISP_MOD_FE0];
} else {
reg_base = gdisp.init_para.reg_base[DISP_MOD_FE1];
}
for(i=8; i<0xa18; i+=4) {
value = sys_get_wvalue(addr + i);
sys_put_wvalue(reg_base + i,value);
}
value = sys_get_wvalue(addr);
sys_put_wvalue(reg_base,value);
value = sys_get_wvalue(addr + 4);
sys_put_wvalue(reg_base + 4,value);
return 0;
}
__s32 BSP_disp_restore_tvec_reg(__u32 sel ,__u32 addr)
{
__u32 i = 0;
__u32 value = 0;
__u32 reg_base = 0;
if(sel == 0)
{
reg_base = gdisp.init_para.base_tvec0;
}
else
{
reg_base = gdisp.init_para.base_tvec1;
}
for(i=8; i<0x210; i+=4)
{
value = sys_get_wvalue(addr + i);
sys_put_wvalue(reg_base + i,value);
}
value = sys_get_wvalue(addr);
sys_put_wvalue(reg_base,value);
value = sys_get_wvalue(addr + 4);
sys_put_wvalue(reg_base + 4,value);
value = sys_get_wvalue(addr + 24);
sys_put_wvalue(reg_base + 24, value);
return 0;
}
__s32 Disp_lcdc_pin_cfg(__u32 sel, __disp_output_type_t out_type, __u32 bon)
{
if(out_type == DISP_OUTPUT_TYPE_LCD)
{
__hdle lcd_pin_hdl;
int i;
for(i=0; i<28; i++)
{
if(gdisp.screen[sel].lcd_cfg.lcd_io_used[i])
{
user_gpio_set_t gpio_info[1];
memcpy(gpio_info, &(gdisp.screen[sel].lcd_cfg.lcd_io[i]), sizeof(user_gpio_set_t));
if(!bon)
{
gpio_info->mul_sel = 0;
}
else
{
if((gpanel_info[sel].lcd_if == 3) && (gpio_info->mul_sel==2))
{
gpio_info->mul_sel = 3;
}
}
lcd_pin_hdl = OSAL_GPIO_Request(gpio_info, 1);
OSAL_GPIO_Release(lcd_pin_hdl, 2);
}
}
}
else if(out_type == DISP_OUTPUT_TYPE_VGA)
{
__u32 reg_start = 0;
__u32 tmp = 0;
if(sel == 0)
{
reg_start = gdisp.init_para.base_pioc+0x6c;
}
else
{
reg_start = gdisp.init_para.base_pioc+0xfc;
}
if(bon)
{
tmp = sys_get_wvalue(reg_start + 0x0c) & 0xffff00ff;
sys_put_wvalue(reg_start + 0x0c,tmp | 0x00002200);
}
else
{
tmp = sys_get_wvalue(reg_start + 0x0c) & 0xffff00ff;
sys_put_wvalue(reg_start + 0x0c,tmp);
}
}
return DIS_SUCCESS;
}
//////////////////////////////////////// back light ////////////////////////////////////////////////////////////////////
static void LCD_bl_open(__u32 sel)
{
__u32 tmp;
__lcd_panel_init_para_t para;
LCD_get_init_para(¶);
// PWM enable
tmp = sys_get_wvalue(para.base_ccmu+0xe0);
tmp |= (1<<4);
sys_put_wvalue(para.base_ccmu+0xe0,tmp);
// GPIO_O_1_EN-BL, PA5 set to 1
/*
tmp = sys_get_wvalue(para.base_pioc + 0x10);
tmp |= 0x00000020;//set bit5
sys_put_wvalue(para.base_pioc+0x10, tmp);
tmp = sys_get_wvalue(para.base_pioc+0x00);
tmp &= 0xff8fffff;
sys_put_wvalue(para.base_pioc+0x00,tmp | (1<<20));//bit22:20, 1:output
tmp = sys_get_wvalue(para.base_pioc + 0x10);
tmp |= 0x00000020;//set bit5
sys_put_wvalue(para.base_pioc+0x10, tmp);
*/
}
static void LCD_bl_close(__u32 sel)
{
__u32 tmp;
__lcd_panel_init_para_t para;
LCD_get_init_para(¶);
/*
// GPIO_O_1_EN-BL, PA5 set to 0
tmp = sys_get_wvalue(para.base_pioc + 0x10);
tmp &= 0xffffffdf;//clear bit5
sys_put_wvalue(para.base_pioc+0x10, tmp);
tmp = sys_get_wvalue(para.base_pioc+0x00);
tmp &= 0xff8fffff;
sys_put_wvalue(para.base_pioc+0x00,tmp | (1<<20));//bit22:20, 1:output
tmp = sys_get_wvalue(para.base_pioc + 0x10);
tmp &= 0xffffffdf;//clear bit5
sys_put_wvalue(para.base_pioc+0x10, tmp);
*/
// PWM disable
tmp = sys_get_wvalue(para.base_ccmu+0xe0);
tmp &= (~(1<<4));
sys_put_wvalue(para.base_ccmu+0xe0,tmp);
}
__s32 DRV_DISP_Init(void)
{
__disp_bsp_init_para para;
init_waitqueue_head(&g_fbi.wait[0]);
init_waitqueue_head(&g_fbi.wait[1]);
g_fbi.wait_count[0] = 0;
g_fbi.wait_count[1] = 0;
memset(¶, 0, sizeof(__disp_bsp_init_para));
para.base_image0 = (__u32)g_fbi.base_image0;
para.base_image1 = (__u32)g_fbi.base_image1;
para.base_scaler0 = (__u32)g_fbi.base_scaler0;
para.base_scaler1 = (__u32)g_fbi.base_scaler1;
para.base_lcdc0 = (__u32)g_fbi.base_lcdc0;
para.base_lcdc1 = (__u32)g_fbi.base_lcdc1;
para.base_tvec0 = (__u32)g_fbi.base_tvec0;
para.base_tvec1 = (__u32)g_fbi.base_tvec1;
para.base_ccmu = (__u32)g_fbi.base_ccmu;
para.base_sdram = (__u32)g_fbi.base_sdram;
para.base_pioc = (__u32)g_fbi.base_pioc;
para.base_pwm = (__u32)g_fbi.base_pwm;
para.disp_int_process = DRV_disp_int_process;
memset(&g_disp_drv, 0, sizeof(__disp_drv_t));
sys_put_wvalue(0xf1c20118, 1<<19);
BSP_disp_init(¶);
BSP_disp_open();
return 0;
}
s32 fb_draw_colorbar(u32 base, u32 width, u32 height, struct fb_var_screeninfo *var)
{
u32 i=0, j=0;
if(!base)
return -1;
for(i = 0; i<height; i++) {
for(j = 0; j<width/4; j++) {
u32 offset = 0;
if(var->bits_per_pixel == 32) {
offset = width * i + j;
sys_put_wvalue(base + offset*4, (((1<<var->transp.length)-1)<<var->transp.offset) | (((1<<var->red.length)-1)<<var->red.offset));
offset = width * i + j + width/4;
sys_put_wvalue(base + offset*4, (((1<<var->transp.length)-1)<<var->transp.offset) | (((1<<var->green.length)-1)<<var->green.offset));
offset = width * i + j + width/4*2;
sys_put_wvalue(base + offset*4, (((1<<var->transp.length)-1)<<var->transp.offset) | (((1<<var->blue.length)-1)<<var->blue.offset));
offset = width * i + j + width/4*3;
sys_put_wvalue(base + offset*4, (((1<<var->transp.length)-1)<<var->transp.offset) | (((1<<var->red.length)-1)<<var->red.offset) | (((1<<var->green.length)-1)<<var->green.offset));
}
#if 0
else if(var->bits_per_pixel == 16) {
offset = width * i + j;
sys_put_hvalue(base + offset*2, (((1<<var->transp.length)-1)<<var->transp.offset) | (((1<<var->red.length)-1)<<var->red.offset));
offset = width * i + j + width/4;
sys_put_hvalue(base + offset*2, (((1<<var->transp.length)-1)<<var->transp.offset) | (((1<<var->green.length)-1)<<var->green.offset));
offset = width * i + j + width/4*2;
sys_put_hvalue(base + offset*2, (((1<<var->transp.length)-1)<<var->transp.offset) | (((1<<var->blue.length)-1)<<var->blue.offset));
offset = width * i + j + width/4*3;
sys_put_hvalue(base + offset*2, (((1<<var->transp.length)-1)<<var->transp.offset) | (((1<<var->red.length)-1)<<var->red.offset) | (((1<<var->green.length)-1)<<var->green.offset));
}
#endif
}
}
return 0;
}
//lcd_pwm_div = log2(24K/(16*pwm_freq));
__s32 Disp_pwm_cfg(__u32 sel)
{
__u32 tmp;
__u32 pwm_div;
__u8 lcd_pwm_div = 0x04;
__u32 i;
__u32 mul_val = 1;
__u32 pwm_freq = gpanel_info[sel].lcd_pwm_freq;
__u32 PWM_SOUCE_FREQ = 24000;
__u32 PWM_LEVEL = 16;
if(pwm_freq)
{
pwm_div = (PWM_SOUCE_FREQ/(PWM_LEVEL * pwm_freq));
}
else
{
pwm_div = 16;
}
for(i = 0;i <= 12;i++)
{
if(pwm_div <= mul_val)
{
lcd_pwm_div = i;
break;
}
mul_val = mul_val * 2;
}
tmp = sys_get_wvalue(gdisp.init_para.base_ccmu+0xe0);
tmp |= ((1<<6) | (1<<5) | lcd_pwm_div);//bit6:gatting the special clock for pwm0; bit5:pwm0 active state is high level
sys_put_wvalue(gdisp.init_para.base_ccmu+0xe0,tmp);
sys_put_wvalue(gdisp.init_para.base_ccmu+0xe4,0x000f000c);
tmp = sys_get_wvalue(gdisp.init_para.base_pioc+0x24);
tmp &= 0xfffff8ff;
sys_put_wvalue(gdisp.init_para.base_pioc+0x24,tmp | (2<<8));//pwm io,PB2, bit10:8
return DIS_SUCCESS;
}
static __s32 pwm_write_reg(__u32 offset, __u32 value)
{
sys_put_wvalue(gdisp.init_para.base_pwm + offset, value);
#ifdef CONFIG_ARCH_SUN4I
LCD_delay_ms(20);
#endif
return 0;
}
static void LCD_bl_close(__u32 sel)
{
__u32 tmp;
__lcd_panel_init_para_t para;
LCD_get_init_para(¶);
tmp = sys_get_wvalue(para.base_timer+0xa0);
tmp &= (~(1<<4));
sys_put_wvalue(para.base_timer+0xa0,tmp);
}
static void LCD_power_off(__u32 sel)//PH27,0 active
{
__u32 tmp = 0;
__lcd_panel_init_para_t para;
LCD_get_init_para(¶);
// LCD-PWR, PH27 set to 1
tmp = sys_get_wvalue(para.base_pioc + 0x10c);
tmp |= 0x08000000;//set bit27
sys_put_wvalue(para.base_pioc+0x10c, tmp);
tmp = sys_get_wvalue(para.base_pioc+0x108);
tmp &= 0xffff8fff;
sys_put_wvalue(para.base_pioc+0x108,tmp | (1<<12));//bit18:16, 1:output
tmp = sys_get_wvalue(para.base_pioc + 0x10c);
tmp |= 0x08000000;//set bit27
sys_put_wvalue(para.base_pioc+0x10c, tmp);
}
__s32 iep_deu_resume (__u32 sel)//restore register
{
__u32 i;
__u32 reg_val;
if(deu_reg_bak[sel]) {
for(i=4; i<0x60; i+=4) {
reg_val = sys_get_wvalue(deu_reg_bak[sel] + i);
sys_put_wvalue(DEU_EBIOS_Get_Reg_Base(sel) + i,reg_val);
}
reg_val = sys_get_wvalue(deu_reg_bak[sel]);
sys_put_wvalue(DEU_EBIOS_Get_Reg_Base(sel),reg_val);
#if defined(__LINUX_OSAL__)
kfree((void*)deu_reg_bak[sel]);
deu_reg_bak[sel] = 0;
#endif
}
return 0;
}
__s32 iep_drc_resume (__u32 sel)//restore register
{
__u32 i;
__u32 reg_val;
if(drc_reg_bak[sel])
{
for(i=4; i<0x3fc; i+=4) {
reg_val = sys_get_wvalue(drc_reg_bak[sel] + i);
sys_put_wvalue(DRC_EBIOS_Get_Reg_Base(sel) + i,reg_val);
}
reg_val = sys_get_wvalue(drc_reg_bak[sel]);
sys_put_wvalue(DRC_EBIOS_Get_Reg_Base(sel),reg_val);
#if defined(__LINUX_OSAL__)
kfree((void*)drc_reg_bak[sel]);
drc_reg_bak[sel] = 0;
#else
OSAL_PhyFree((void *)drc_reg_bak[sel], sizeof(__u32)*0x3fc);
#endif
}
return 0;
}
__s32 iep_drc_suspend(__u32 sel)//save register
{
__u32 i,reg_val;
#if defined(__LINUX_OSAL__)
drc_reg_bak[sel] = (__u32)kmalloc(sizeof(__u32)*0x3fc,GFP_KERNEL | __GFP_ZERO);
#endif
if(drc_reg_bak[sel]) {
for(i=0; i<0x3fc; i+=4) {
/* save register */
reg_val = sys_get_wvalue(DRC_EBIOS_Get_Reg_Base(sel) +i);
sys_put_wvalue(drc_reg_bak[sel]+i, reg_val);
}
}
return 0;
}
__s32 fb_draw_gray_pictures(__u32 base, __u32 width, __u32 height, struct fb_var_screeninfo *var)
{
__u32 time = 0;
for(time = 0; time<18; time++) {
__u32 i=0, j=0;
for(i = 0; i<height; i++) {
for(j = 0; j<width; j++) {
__u32 addr = base + (i*width+ j)*4;
__u32 value = (0xff<<24) | ((time*15)<<16) | ((time*15)<<8) | (time*15);
sys_put_wvalue(addr, value);
}
}
}
return 0;
}
__s32 bsp_disp_store_image_reg(__u32 screen_id, __u32 addr)
{
__u32 i = 0;
__u32 value = 0;
__u32 reg_base = 0;
if(screen_id == 0) {
reg_base = gdisp.init_para.reg_base[DISP_MOD_BE0];
} else {
reg_base = gdisp.init_para.reg_base[DISP_MOD_BE1];
}
for(i=0; i<0xe00 - 0x800; i+=4) {
value = sys_get_wvalue(reg_base + 0x800 + i);
sys_put_wvalue(addr + i, value);
}
return 0;
}
//setting: 0, 1, 2,.... 14, 15
//pol==0: 1, 2, 3,.... 15, 0
//pol==1: 0, 15, 14, ... 2, 1
__s32 BSP_disp_lcd_set_bright(__u32 sel, __disp_lcd_bright_t bright)
{
if(gdisp.screen[sel].status & LCD_ON)
{
__u32 value = 0;
__u32 tmp;
if(gpanel_info[sel].lcd_pwm_pol == 0)
{
if(bright == DISP_LCD_BRIGHT_LEVEL15)
{
value = 0;
}
else
{
value = bright + 1;
}
}
else
{
if(bright == DISP_LCD_BRIGHT_LEVEL0)
{
value = 0;
}
else
{
value = 16 - bright;
}
}
tmp = sys_get_wvalue(gdisp.init_para.base_ccmu+0xe4);
sys_put_wvalue(gdisp.init_para.base_ccmu+0xe4,(tmp & 0xffff0000) | value);
}
return DIS_SUCCESS;
}
static __u32 sunxi_pwm_write_reg(__u32 offset, __u32 value)
{
sys_put_wvalue(SUNXI_PWM_VBASE + offset, value);
return 0;
}
//pwm pin
//pB2: 2:pwm0
//pI3: 2:pwm1
__s32 Disp_lcdc_pin_cfg(__u32 sel, __disp_output_type_t out_type, __u32 bon) //lcd pin, pwm pin
{
__u32 tmp = 0;
if(bon)
{
if(sel == 0)
{
switch(out_type)
{
case DISP_OUTPUT_TYPE_LCD:
case DISP_OUTPUT_TYPE_HDMI:
sys_put_wvalue(gdisp.init_para.base_pioc+0x6c,0x22222222);
sys_put_wvalue(gdisp.init_para.base_pioc+0x70,0x22222222);
sys_put_wvalue(gdisp.init_para.base_pioc+0x74,0x22222222);
sys_put_wvalue(gdisp.init_para.base_pioc+0x78,0x00002222);
break;
case DISP_OUTPUT_TYPE_VGA:
tmp = sys_get_wvalue(gdisp.init_para.base_pioc+0x6c) & 0xffff00ff;
sys_put_wvalue(gdisp.init_para.base_pioc+0x6c,tmp | 0x00002200);
break;
default:
break;
}
}
else if(sel == 1)
{
switch(out_type)
{
case DISP_OUTPUT_TYPE_LCD:
case DISP_OUTPUT_TYPE_HDMI:
sys_put_wvalue(gdisp.init_para.base_pioc+0x6c,0x44444444);
sys_put_wvalue(gdisp.init_para.base_pioc+0x70,0x44444444);
sys_put_wvalue(gdisp.init_para.base_pioc+0x74,0x44444444);
sys_put_wvalue(gdisp.init_para.base_pioc+0x78,0x00004444);
break;
case DISP_OUTPUT_TYPE_VGA:
tmp = sys_get_wvalue(gdisp.init_para.base_pioc+0x6c) & 0xffff00ff;
sys_put_wvalue(gdisp.init_para.base_pioc+0x6c,tmp | 0x00004400);
break;
default:
break;
}
}
}
else
{
sys_put_wvalue(gdisp.init_para.base_pioc+0x6c,0x00000000);
sys_put_wvalue(gdisp.init_para.base_pioc+0x70,0x00000000);
sys_put_wvalue(gdisp.init_para.base_pioc+0x74,0x00000000);
sys_put_wvalue(gdisp.init_para.base_pioc+0x78,0x00000000);
}
return DIS_SUCCESS;
}
uint sunxi_pwm_write_reg(uint offset, uint value)
{
sys_put_wvalue(PWM03_BASE + offset, value);
return 0;
}
__s32 audio_config(void)
{
__s32 i;
__inf("audio_config, sample_rate:%d\n", audio_info.sample_rate);
HDMI_WUINT32(0x040,0x00000000);
HDMI_WUINT32(0x040,0x40000000);
while(HDMI_RUINT32(0x040) != 0);
HDMI_WUINT32(0x040,0x40000000);
while(HDMI_RUINT32(0x040) != 0);
if(!audio_info.audio_en)
{
return 0;
}
i = get_audio_info(audio_info.sample_rate);
if(i == -1)
{
return 0;
}
if(audio_info.channel_num == 1)
{
HDMI_WUINT32(0x044,0x00000000); //audio fifo rst and select ddma, 2 ch 16bit pcm
HDMI_WUINT32(0x048,0x00000000); //ddma,pcm layout0 1ch
HDMI_WUINT32(0x04c,0x76543200);
HDMI_WUINT32(0x0A0,0x710a0184); //audio infoframe head
HDMI_WUINT32(0x0A4,0x00000000); //CA = 0X1F
HDMI_WUINT32(0x0A8,0x00000000);
HDMI_WUINT32(0x0Ac,0x00000000);
}else if(audio_info.channel_num == 2)
{
HDMI_WUINT32(0x044,0x00000000); //audio fifo rst and select ddma, 2 ch 16bit pcm
if(audio_info.data_raw == 0)
{
HDMI_WUINT32(0x048,0x00000001); //ddma,pcm layout0 2ch
}
else
{
HDMI_WUINT32(0x048,0x01000001); //ddma,raw layout0 2ch
}
HDMI_WUINT32(0x04c,0x76543210);
HDMI_WUINT32(0x0A0,0x710a0184); //audio infoframe head
HDMI_WUINT32(0x0A4,0x00000000); //CA = 0X1F
HDMI_WUINT32(0x0A8,0x00000000);
HDMI_WUINT32(0x0Ac,0x00000000);
}else if(audio_info.channel_num == 8)
{
HDMI_WUINT32(0x044,0x00000000); //audio fifo rst and select ddma, 2 ch 16bit pcm
HDMI_WUINT32(0x048,0x0000000f); //ddma,pcm layout1 8ch
HDMI_WUINT32(0x04c,0x76543210);
HDMI_WUINT32(0x0A0,0x520a0184); //audio infoframe head
HDMI_WUINT32(0x0A4,0x1F000000); //CA = 0X1F
HDMI_WUINT32(0x0A8,0x00000000);
HDMI_WUINT32(0x0Ac,0x00000000);
}else
{
__wrn("unkonwn num_ch:%d\n", audio_info.channel_num);
}
HDMI_WUINT32(0x050,audio_info.CTS ); //CTS and N
HDMI_WUINT32(0x054,audio_info.ACR_N );
HDMI_WUINT32(0x058,audio_info.CH_STATUS0 );
HDMI_WUINT32(0x05c,audio_info.CH_STATUS1 );
HDMI_WUINT32(0x040,0x80000000);
HDMI_WUINT32(0x004,0x80000000);
//for audio test
#if 0
//dedicated dma setting aw1623 env
sys_put_wvalue(0xf1c023a4,0x40c00000); //ddma ch5 seting from addr =0x40c00000
sys_put_wvalue(0xf1c023a8,0x00000000); //des =0
sys_put_wvalue(0xf1c023ac,0x01f00000); //byte to trans
sys_put_wvalue(0xf1c023b8,(31<<24) +(7<<16) + (31<<8) +(7<<0)); //data block and wait cycle
sys_put_wvalue(0xf1c023a0,0xa4b80481); //from src0 to des1,continous mode
#endif
return 0;
}
static __s32 pwm_write_reg(__u32 offset, __u32 value)
{
sys_put_wvalue(gdisp.init_para.base_pwm+offset, value);
return 0;
}
static void
Lcd_Panel_Parameter_Check(__u32 sel)
{
__panel_para_t *info;
__u32 cycle_num = 1;
__u32 Lcd_Panel_Err_Flag = 0;
__u32 Lcd_Panel_Wrn_Flag = 0;
__u32 Disp_Driver_Bug_Flag = 0;
__u32 lcd_fclk_frq;
__u32 lcd_clk_div;
info = &(gpanel_info[sel]);
if (info->lcd_if == 0 && info->lcd_hv_if == 1 &&
info->lcd_hv_smode == 0)
cycle_num = 3;
else if (info->lcd_if == 0 && info->lcd_hv_if == 1 &&
info->lcd_hv_smode == 1)
cycle_num = 2;
else if (info->lcd_if == 1 && info->lcd_cpu_if == 1)
cycle_num = 3;
else if (info->lcd_if == 1 && info->lcd_cpu_if == 2)
cycle_num = 2;
else if (info->lcd_if == 1 && info->lcd_cpu_if == 3)
cycle_num = 2;
else if (info->lcd_if == 1 && info->lcd_cpu_if == 5)
cycle_num = 2;
else if (info->lcd_if == 1 && info->lcd_cpu_if == 6)
cycle_num = 3;
else if (info->lcd_if == 1 && info->lcd_cpu_if == 7)
cycle_num = 2;
else
cycle_num = 1;
if (info->lcd_hbp > info->lcd_hv_hspw)
;
else
Lcd_Panel_Err_Flag |= BIT0;
if (info->lcd_vbp > info->lcd_hv_vspw)
;
else
Lcd_Panel_Err_Flag |= BIT1;
if (info->lcd_ht >= (info->lcd_hbp + info->lcd_x * cycle_num + 4))
;
else
Lcd_Panel_Err_Flag |= BIT2;
if ((info->lcd_vt / 2) >= (info->lcd_vbp + info->lcd_y + 2))
;
else
Lcd_Panel_Err_Flag |= BIT3;
lcd_clk_div = TCON0_get_dclk_div(sel);
if (lcd_clk_div >= 6) {
;
} else if ((lcd_clk_div == 5) || (lcd_clk_div == 4) ||
(lcd_clk_div == 2)) {
if ((info->lcd_io_cfg0 != 0x00000000) &&
(info->lcd_io_cfg0 != 0x04000000))
Lcd_Panel_Err_Flag |= BIT10;
} else
Disp_Driver_Bug_Flag |= 1;
if ((info->lcd_if == 1 && info->lcd_cpu_if == 0) ||
(info->lcd_if == 3 && info->lcd_lvds_bitwidth == 1)) {
if (info->lcd_frm != 1)
Lcd_Panel_Wrn_Flag |= BIT0;
} else if (info->lcd_if == 1 && info->lcd_cpu_if == 4) {
if (info->lcd_frm != 2)
Lcd_Panel_Wrn_Flag |= BIT1;
}
lcd_fclk_frq = (info->lcd_dclk_freq * 1000 * 1000) /
((info->lcd_vt / 2) * info->lcd_ht);
if (lcd_fclk_frq < 50 || lcd_fclk_frq > 70)
Lcd_Panel_Wrn_Flag |= BIT2;
if (Lcd_Panel_Err_Flag != 0 || Lcd_Panel_Wrn_Flag != 0) {
if (Lcd_Panel_Err_Flag != 0) {
__u32 i;
for (i = 0; i < 200; i++)
DE_WRN("*** Lcd in danger...\n");
}
DE_WRN("*******************************************************"
"**********\n");
DE_WRN("***\n");
DE_WRN("*** LCD Panel Parameter Check\n");
DE_WRN("***\n");
DE_WRN("*** by dulianping\n");
DE_WRN("***\n");
DE_WRN("*******************************************************"
"**********\n");
DE_WRN("***\n");
DE_WRN("*** Interface:");
if (info->lcd_if == 0 && info->lcd_hv_if == 0) {
DE_WRN("*** Parallel HV Panel\n");
} else if (info->lcd_if == 0 && info->lcd_hv_if == 1) {
DE_WRN("*** Serial HV Panel\n");
} else if (info->lcd_if == 0 && info->lcd_hv_if == 2) {
DE_WRN("*** Serial YUV Panel\n");
} else if (info->lcd_if == 3 && info->lcd_lvds_bitwidth == 0) {
DE_WRN("*** 24Bit LVDS Panel\n");
} else if (info->lcd_if == 3 && info->lcd_lvds_bitwidth == 1) {
DE_WRN("*** 18Bit LVDS Panel\n");
} else if (info->lcd_if == 1 && info->lcd_cpu_if == 0) {
DE_WRN("*** 18Bit CPU Panel\n");
} else if (info->lcd_if == 1 && info->lcd_cpu_if == 4) {
DE_WRN("*** 16Bit CPU Panel\n");
} else {
DE_WRN("\n");
DE_WRN("*** lcd_if: %d\n", info->lcd_if);
DE_WRN("*** lcd_hv_if: %d\n", info->lcd_hv_if);
DE_WRN("*** lcd_cpu_if: %d\n", info->lcd_cpu_if);
}
if (info->lcd_frm == 0)
DE_WRN("*** Lcd Frm Disable\n");
else if (info->lcd_frm == 1)
DE_WRN("*** Lcd Frm to RGB666\n");
else if (info->lcd_frm == 2)
DE_WRN("*** Lcd Frm to RGB565\n");
DE_WRN("***\n");
DE_WRN("*** Timing:\n");
DE_WRN("*** lcd_x: %d\n", info->lcd_x);
DE_WRN("*** lcd_y: %d\n", info->lcd_y);
DE_WRN("*** lcd_ht: %d\n", info->lcd_ht);
DE_WRN("*** lcd_hbp: %d\n", info->lcd_hbp);
DE_WRN("*** lcd_vt: %d\n", info->lcd_vt);
DE_WRN("*** lcd_vbp: %d\n", info->lcd_vbp);
DE_WRN("*** lcd_hspw: %d\n", info->lcd_hv_hspw);
DE_WRN("*** lcd_vspw: %d\n", info->lcd_hv_vspw);
DE_WRN("*** lcd_frame_frq: %dHz\n", lcd_fclk_frq);
/* Print Error */
DE_WRN("***\n");
if (Lcd_Panel_Err_Flag & BIT0)
DE_WRN("*** Err01: Violate \"lcd_hbp > lcd_hspw\"\n");
if (Lcd_Panel_Err_Flag & BIT1)
DE_WRN("*** Err02: Violate \"lcd_vbp > lcd_vspw\"\n");
if (Lcd_Panel_Err_Flag & BIT2)
DE_WRN("*** Err03: Violate \"lcd_ht >= "
"(lcd_hbp+lcd_x*%d+4)\"\n", cycle_num);
if (Lcd_Panel_Err_Flag & BIT3)
DE_WRN("*** Err04: Violate \"(lcd_vt/2) >= "
"(lcd_vbp+lcd_y+2)\"\n");
if (Lcd_Panel_Err_Flag & BIT10)
DE_WRN("*** Err10: Violate \"lcd_io_cfg0\", "
"use \"0x00000000\" or \"0x04000000\"");
if (Lcd_Panel_Wrn_Flag & BIT0)
DE_WRN("*** WRN01: Recommend \"lcd_frm = 1\"\n");
if (Lcd_Panel_Wrn_Flag & BIT1)
DE_WRN("*** WRN02: Recommend \"lcd_frm = 2\"\n");
if (Lcd_Panel_Wrn_Flag & BIT2)
DE_WRN("*** WRN03: Recommend \"lcd_dclk_frq = %d\"\n",
((info->lcd_vt / 2) * info->lcd_ht) * 60 /
(1000 * 1000));
DE_WRN("***\n");
if (Lcd_Panel_Err_Flag != 0) {
__u32 image_base_addr;
__u32 reg_value = 0;
image_base_addr = DE_Get_Reg_Base(sel);
/* set background color */
sys_put_wvalue(image_base_addr + 0x804, 0xffff00ff);
reg_value = sys_get_wvalue(image_base_addr + 0x800);
/* close all layer */
sys_put_wvalue(image_base_addr + 0x800,
reg_value & 0xfffff0ff);
LCD_delay_ms(2000);
/* set background color */
sys_put_wvalue(image_base_addr + 0x804, 0x00000000);
/* open layer */
sys_put_wvalue(image_base_addr + 0x800, reg_value);
DE_WRN("*** Try new parameters, you can make it "
"pass!\n");
}
DE_WRN("*** LCD Panel Parameter Check End\n");
DE_WRN("*******************************************************"
"**********\n");
}
}
