static void digic_init(Object *obj) { DigicState *s = DIGIC(obj); DeviceState *dev; int i; object_initialize(&s->cpu, sizeof(s->cpu), "arm946-" TYPE_ARM_CPU); object_property_add_child(obj, "cpu", OBJECT(&s->cpu), NULL); for (i = 0; i < DIGIC4_NB_TIMERS; i++) { #define DIGIC_TIMER_NAME_MLEN 11 char name[DIGIC_TIMER_NAME_MLEN]; object_initialize(&s->timer[i], sizeof(s->timer[i]), TYPE_DIGIC_TIMER); dev = DEVICE(&s->timer[i]); qdev_set_parent_bus(dev, sysbus_get_default()); snprintf(name, DIGIC_TIMER_NAME_MLEN, "timer[%d]", i); object_property_add_child(obj, name, OBJECT(&s->timer[i]), NULL); } object_initialize(&s->uart, sizeof(s->uart), TYPE_DIGIC_UART); dev = DEVICE(&s->uart); qdev_set_parent_bus(dev, sysbus_get_default()); object_property_add_child(obj, "uart", OBJECT(&s->uart), NULL); }
void sysbus_init_child_obj(Object *parent, const char *childname, void *child, size_t childsize, const char *childtype) { object_initialize_child(parent, childname, child, childsize, childtype, &error_abort, NULL); qdev_set_parent_bus(DEVICE(child), sysbus_get_default()); }
static void macio_instance_init(Object *obj) { MacIOState *s = MACIO(obj); memory_region_init(&s->bar, obj, "macio", 0x80000); object_initialize(&s->cuda, sizeof(s->cuda), TYPE_CUDA); qdev_set_parent_bus(DEVICE(&s->cuda), sysbus_get_default()); object_property_add_child(obj, "cuda", OBJECT(&s->cuda), NULL); object_initialize(&s->dbdma, sizeof(s->dbdma), TYPE_MAC_DBDMA); qdev_set_parent_bus(DEVICE(&s->dbdma), sysbus_get_default()); object_property_add_child(obj, "dbdma", OBJECT(&s->dbdma), NULL); object_initialize(&s->escc, sizeof(s->escc), TYPE_ESCC); qdev_set_parent_bus(DEVICE(&s->escc), sysbus_get_default()); object_property_add_child(obj, "escc", OBJECT(&s->escc), NULL); }
static void bcm2836_init(Object *obj) { BCM2836State *s = BCM2836(obj); object_initialize(&s->control, sizeof(s->control), TYPE_BCM2836_CONTROL); object_property_add_child(obj, "control", OBJECT(&s->control), NULL); qdev_set_parent_bus(DEVICE(&s->control), sysbus_get_default()); object_initialize(&s->peripherals, sizeof(s->peripherals), TYPE_BCM2835_PERIPHERALS); object_property_add_child(obj, "peripherals", OBJECT(&s->peripherals), &error_abort); object_property_add_alias(obj, "board-rev", OBJECT(&s->peripherals), "board-rev", &error_abort); object_property_add_alias(obj, "vcram-size", OBJECT(&s->peripherals), "vcram-size", &error_abort); qdev_set_parent_bus(DEVICE(&s->peripherals), sysbus_get_default()); }
static void init_sysbus_child(Object *parent, const char *childname, void *child, size_t childsize, const char *childtype) { object_initialize(child, childsize, childtype); object_property_add_child(parent, childname, OBJECT(child), &error_abort); qdev_set_parent_bus(DEVICE(child), sysbus_get_default()); }
static MemoryRegion *make_fpgaio(MPS2TZMachineState *mms, void *opaque, const char *name, hwaddr size) { MPS2FPGAIO *fpgaio = opaque; object_initialize(fpgaio, sizeof(mms->fpgaio), TYPE_MPS2_FPGAIO); qdev_set_parent_bus(DEVICE(fpgaio), sysbus_get_default()); object_property_set_bool(OBJECT(fpgaio), true, "realized", &error_fatal); return sysbus_mmio_get_region(SYS_BUS_DEVICE(fpgaio), 0); }
static void stm32f205_soc_initfn(Object *obj) { STM32F205State *s = STM32F205_SOC(obj); int i; object_initialize(&s->syscfg, sizeof(s->syscfg), TYPE_STM32F2XX_SYSCFG); qdev_set_parent_bus(DEVICE(&s->syscfg), sysbus_get_default()); for (i = 0; i < STM_NUM_USARTS; i++) { object_initialize(&s->usart[i], sizeof(s->usart[i]), TYPE_STM32F2XX_USART); qdev_set_parent_bus(DEVICE(&s->usart[i]), sysbus_get_default()); } for (i = 0; i < STM_NUM_TIMERS; i++) { object_initialize(&s->timer[i], sizeof(s->timer[i]), TYPE_STM32F2XX_TIMER); qdev_set_parent_bus(DEVICE(&s->timer[i]), sysbus_get_default()); } }
static void xlnx_zynqmp_pmu_init(MachineState *machine) { XlnxZynqMPPMUSoCState *pmu = g_new0(XlnxZynqMPPMUSoCState, 1); MemoryRegion *address_space_mem = get_system_memory(); MemoryRegion *pmu_rom = g_new(MemoryRegion, 1); MemoryRegion *pmu_ram = g_new(MemoryRegion, 1); XlnxZynqMPIPI *ipi[XLNX_ZYNQMP_PMU_NUM_IPIS]; qemu_irq irq[32]; int i; /* Create the ROM */ memory_region_init_rom(pmu_rom, NULL, "xlnx-zynqmp-pmu.rom", XLNX_ZYNQMP_PMU_ROM_SIZE, &error_fatal); memory_region_add_subregion(address_space_mem, XLNX_ZYNQMP_PMU_ROM_ADDR, pmu_rom); /* Create the RAM */ memory_region_init_ram(pmu_ram, NULL, "xlnx-zynqmp-pmu.ram", machine->ram_size, &error_fatal); memory_region_add_subregion(address_space_mem, XLNX_ZYNQMP_PMU_RAM_ADDR, pmu_ram); /* Create the PMU device */ object_initialize(pmu, sizeof(XlnxZynqMPPMUSoCState), TYPE_XLNX_ZYNQMP_PMU_SOC); object_property_add_child(OBJECT(machine), "pmu", OBJECT(pmu), &error_abort); object_property_set_bool(OBJECT(pmu), true, "realized", &error_fatal); for (i = 0; i < 32; i++) { irq[i] = qdev_get_gpio_in(DEVICE(&pmu->intc), i); } /* Create and connect the IPI device */ for (i = 0; i < XLNX_ZYNQMP_PMU_NUM_IPIS; i++) { ipi[i] = g_new0(XlnxZynqMPIPI, 1); object_initialize(ipi[i], sizeof(XlnxZynqMPIPI), TYPE_XLNX_ZYNQMP_IPI); qdev_set_parent_bus(DEVICE(ipi[i]), sysbus_get_default()); } for (i = 0; i < XLNX_ZYNQMP_PMU_NUM_IPIS; i++) { object_property_set_bool(OBJECT(ipi[i]), true, "realized", &error_abort); sysbus_mmio_map(SYS_BUS_DEVICE(ipi[i]), 0, ipi_addr[i]); sysbus_connect_irq(SYS_BUS_DEVICE(ipi[i]), 0, irq[ipi_irq[i]]); } /* Load the kernel */ microblaze_load_kernel(&pmu->cpu, XLNX_ZYNQMP_PMU_RAM_ADDR, machine->ram_size, machine->initrd_filename, machine->dtb, NULL); }
static void a9mp_priv_initfn(Object *obj) { A9MPPrivState *s = A9MPCORE_PRIV(obj); memory_region_init(&s->container, obj, "a9mp-priv-container", 0x2000); sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->container); object_initialize(&s->scu, sizeof(s->scu), TYPE_A9_SCU); qdev_set_parent_bus(DEVICE(&s->scu), sysbus_get_default()); object_initialize(&s->gic, sizeof(s->gic), TYPE_ARM_GIC); qdev_set_parent_bus(DEVICE(&s->gic), sysbus_get_default()); object_initialize(&s->gtimer, sizeof(s->gtimer), TYPE_A9_GTIMER); qdev_set_parent_bus(DEVICE(&s->gtimer), sysbus_get_default()); object_initialize(&s->mptimer, sizeof(s->mptimer), TYPE_ARM_MPTIMER); qdev_set_parent_bus(DEVICE(&s->mptimer), sysbus_get_default()); object_initialize(&s->wdt, sizeof(s->wdt), TYPE_ARM_MPTIMER); qdev_set_parent_bus(DEVICE(&s->wdt), sysbus_get_default()); }
/* Console hooks */ void goldfish_fb_set_rotation(int rotation) { DeviceState *dev = qdev_find_recursive(sysbus_get_default(), TYPE_GOLDFISH_FB); if (dev) { struct goldfish_fb_state *s = GOLDFISH_FB(dev); DisplaySurface *ds = qemu_console_surface(s->con); s->rotation = rotation; s->need_update = 1; qemu_console_resize(s->con, surface_height(ds), surface_width(ds)); } else { fprintf(stderr,"%s: unable to find FB dev\n", __func__); } }
static void macio_init_ide(MacIOState *s, MACIOIDEState *ide, size_t ide_size, int index) { gchar *name; object_initialize(ide, ide_size, TYPE_MACIO_IDE); qdev_set_parent_bus(DEVICE(ide), sysbus_get_default()); memory_region_add_subregion(&s->bar, 0x1f000 + ((index + 1) * 0x1000), &ide->mem); name = g_strdup_printf("ide[%i]", index); object_property_add_child(OBJECT(s), name, OBJECT(ide), NULL); g_free(name); }
static void mpcore_priv_initfn(Object *obj) { SysBusDevice *sbd = SYS_BUS_DEVICE(obj); ARM11MPCorePriveState *s = ARM11MPCORE_PRIV(obj); memory_region_init(&s->container, OBJECT(s), "mpcore-priv-container", 0x2000); sysbus_init_mmio(sbd, &s->container); object_initialize(&s->scu, sizeof(s->scu), TYPE_ARM11_SCU); qdev_set_parent_bus(DEVICE(&s->scu), sysbus_get_default()); object_initialize(&s->gic, sizeof(s->gic), TYPE_ARM_GIC); qdev_set_parent_bus(DEVICE(&s->gic), sysbus_get_default()); /* Request the legacy 11MPCore GIC behaviour: */ qdev_prop_set_uint32(DEVICE(&s->gic), "revision", 0); object_initialize(&s->mptimer, sizeof(s->mptimer), TYPE_ARM_MPTIMER); qdev_set_parent_bus(DEVICE(&s->mptimer), sysbus_get_default()); object_initialize(&s->wdtimer, sizeof(s->wdtimer), TYPE_ARM_MPTIMER); qdev_set_parent_bus(DEVICE(&s->wdtimer), sysbus_get_default()); }
static void macio_instance_init(Object *obj) { MacIOState *s = MACIO(obj); MemoryRegion *dbdma_mem; memory_region_init(&s->bar, NULL, "macio", 0x80000); object_initialize(&s->cuda, sizeof(s->cuda), TYPE_CUDA); qdev_set_parent_bus(DEVICE(&s->cuda), sysbus_get_default()); object_property_add_child(obj, "cuda", OBJECT(&s->cuda), NULL); s->dbdma = DBDMA_init(&dbdma_mem); memory_region_add_subregion(&s->bar, 0x08000, dbdma_mem); }
static void bcm2835_init(Object *obj) { BCM2835State *s = BCM2835(obj); object_initialize(&s->cpu, sizeof(s->cpu), "arm1176-" TYPE_ARM_CPU); object_property_add_child(obj, "cpu", OBJECT(&s->cpu), &error_abort); object_initialize(&s->peripherals, sizeof(s->peripherals), TYPE_BCM2835_PERIPHERALS); object_property_add_child(obj, "peripherals", OBJECT(&s->peripherals), &error_abort); object_property_add_alias(obj, "vcram-size", OBJECT(&s->peripherals), "vcram-size", &error_abort); qdev_set_parent_bus(DEVICE(&s->peripherals), sysbus_get_default()); }
static MemoryRegion *make_scc(MPS2TZMachineState *mms, void *opaque, const char *name, hwaddr size) { MPS2SCC *scc = opaque; DeviceState *sccdev; MPS2TZMachineClass *mmc = MPS2TZ_MACHINE_GET_CLASS(mms); object_initialize(scc, sizeof(mms->scc), TYPE_MPS2_SCC); sccdev = DEVICE(scc); qdev_set_parent_bus(sccdev, sysbus_get_default()); qdev_prop_set_uint32(sccdev, "scc-cfg4", 0x2); qdev_prop_set_uint32(sccdev, "scc-aid", 0x02000008); qdev_prop_set_uint32(sccdev, "scc-id", mmc->scc_id); object_property_set_bool(OBJECT(scc), true, "realized", &error_fatal); return sysbus_mmio_get_region(SYS_BUS_DEVICE(sccdev), 0); }
static void macio_oldworld_init(Object *obj) { MacIOState *s = MACIO(obj); OldWorldMacIOState *os = OLDWORLD_MACIO(obj); DeviceState *dev; qdev_init_gpio_out(DEVICE(obj), os->irqs, ARRAY_SIZE(os->irqs)); object_initialize(&os->nvram, TYPE_MACIO_NVRAM); dev = DEVICE(&os->nvram); qdev_prop_set_uint32(dev, "size", 0x2000); qdev_prop_set_uint32(dev, "it_shift", 4); object_initialize(&os->ide, TYPE_MACIO_IDE); qdev_set_parent_bus(DEVICE(&os->ide), sysbus_get_default()); memory_region_add_subregion(&s->bar, 0x1f000 + (1 * 0x1000), &os->ide.mem); object_property_add_child(obj, "ide", OBJECT(&os->ide), NULL); }
static void fsl_imx25_init(Object *obj) { FslIMX25State *s = FSL_IMX25(obj); int i; object_initialize(&s->cpu, sizeof(s->cpu), "arm926-" TYPE_ARM_CPU); object_initialize(&s->avic, sizeof(s->avic), TYPE_IMX_AVIC); qdev_set_parent_bus(DEVICE(&s->avic), sysbus_get_default()); object_initialize(&s->ccm, sizeof(s->ccm), TYPE_IMX_CCM); qdev_set_parent_bus(DEVICE(&s->ccm), sysbus_get_default()); for (i = 0; i < FSL_IMX25_NUM_UARTS; i++) { object_initialize(&s->uart[i], sizeof(s->uart[i]), TYPE_IMX_SERIAL); qdev_set_parent_bus(DEVICE(&s->uart[i]), sysbus_get_default()); } for (i = 0; i < FSL_IMX25_NUM_GPTS; i++) { object_initialize(&s->gpt[i], sizeof(s->gpt[i]), TYPE_IMX_GPT); qdev_set_parent_bus(DEVICE(&s->gpt[i]), sysbus_get_default()); } for (i = 0; i < FSL_IMX25_NUM_EPITS; i++) { object_initialize(&s->epit[i], sizeof(s->epit[i]), TYPE_IMX_EPIT); qdev_set_parent_bus(DEVICE(&s->epit[i]), sysbus_get_default()); } object_initialize(&s->fec, sizeof(s->fec), TYPE_IMX_FEC); qdev_set_parent_bus(DEVICE(&s->fec), sysbus_get_default()); for (i = 0; i < FSL_IMX25_NUM_I2CS; i++) { object_initialize(&s->i2c[i], sizeof(s->i2c[i]), TYPE_IMX_I2C); qdev_set_parent_bus(DEVICE(&s->i2c[i]), sysbus_get_default()); } for (i = 0; i < FSL_IMX25_NUM_GPIOS; i++) { object_initialize(&s->gpio[i], sizeof(s->gpio[i]), TYPE_IMX_GPIO); qdev_set_parent_bus(DEVICE(&s->gpio[i]), sysbus_get_default()); } }
static void macio_newworld_init(Object *obj) { MacIOState *s = MACIO(obj); NewWorldMacIOState *ns = NEWWORLD_MACIO(obj); int i; gchar *name; qdev_init_gpio_out(DEVICE(obj), ns->irqs, ARRAY_SIZE(ns->irqs)); for (i = 0; i < 2; i++) { object_initialize(&ns->ide[i], TYPE_MACIO_IDE); qdev_set_parent_bus(DEVICE(&ns->ide[i]), sysbus_get_default()); memory_region_add_subregion(&s->bar, 0x1f000 + ((i + 1) * 0x1000), &ns->ide[i].mem); name = g_strdup_printf("ide[%i]", i); object_property_add_child(obj, name, OBJECT(&ns->ide[i]), NULL); g_free(name); } }
static void a15mp_priv_initfn(Object *obj) { SysBusDevice *sbd = SYS_BUS_DEVICE(obj); A15MPPrivState *s = A15MPCORE_PRIV(obj); DeviceState *gicdev; const char *gictype = "arm_gic"; if (kvm_irqchip_in_kernel()) { gictype = "kvm-arm-gic"; } memory_region_init(&s->container, obj, "a15mp-priv-container", 0x8000); sysbus_init_mmio(sbd, &s->container); object_initialize(&s->gic, sizeof(s->gic), gictype); gicdev = DEVICE(&s->gic); qdev_set_parent_bus(gicdev, sysbus_get_default()); qdev_prop_set_uint32(gicdev, "revision", 2); }
static void platform_bus_create_devtree(PPCE500Params *params, void *fdt, const char *mpic) { gchar *node = g_strdup_printf("/platform@%"PRIx64, params->platform_bus_base); const char platcomp[] = "qemu,platform\0simple-bus"; uint64_t addr = params->platform_bus_base; uint64_t size = params->platform_bus_size; int irq_start = params->platform_bus_first_irq; PlatformBusDevice *pbus; DeviceState *dev; /* Create a /platform node that we can put all devices into */ qemu_fdt_add_subnode(fdt, node); qemu_fdt_setprop(fdt, node, "compatible", platcomp, sizeof(platcomp)); /* Our platform bus region is less than 32bit big, so 1 cell is enough for address and size */ qemu_fdt_setprop_cells(fdt, node, "#size-cells", 1); qemu_fdt_setprop_cells(fdt, node, "#address-cells", 1); qemu_fdt_setprop_cells(fdt, node, "ranges", 0, addr >> 32, addr, size); qemu_fdt_setprop_phandle(fdt, node, "interrupt-parent", mpic); dev = qdev_find_recursive(sysbus_get_default(), TYPE_PLATFORM_BUS_DEVICE); pbus = PLATFORM_BUS_DEVICE(dev); /* We can only create dt nodes for dynamic devices when they're ready */ if (pbus->done_gathering) { PlatformDevtreeData data = { .fdt = fdt, .mpic = mpic, .irq_start = irq_start, .node = node, .pbus = pbus, }; /* Loop through all dynamic sysbus devices and create nodes for them */ foreach_dynamic_sysbus_device(sysbus_device_create_devtree, &data); }
DeviceState *qdev_try_create(BusState *bus, const char *type) { #if 0 DeviceState *dev; if (object_class_by_name(NULL, type) == NULL) { // no need to fix. aq return NULL; } dev = DEVICE(object_new(NULL, type)); // no need to fix. aq if (!dev) { return NULL; } if (!bus) { bus = sysbus_get_default(); } qdev_set_parent_bus(dev, bus); object_unref(OBJECT(dev)); return dev; #endif return NULL; }
static void ast2400_init(Object *obj) { AST2400State *s = AST2400(obj); s->cpu = cpu_arm_init("arm926"); object_initialize(&s->vic, sizeof(s->vic), TYPE_ASPEED_VIC); object_property_add_child(obj, "vic", OBJECT(&s->vic), NULL); qdev_set_parent_bus(DEVICE(&s->vic), sysbus_get_default()); object_initialize(&s->timerctrl, sizeof(s->timerctrl), TYPE_ASPEED_TIMER); object_property_add_child(obj, "timerctrl", OBJECT(&s->timerctrl), NULL); qdev_set_parent_bus(DEVICE(&s->timerctrl), sysbus_get_default()); object_initialize(&s->i2c, sizeof(s->i2c), TYPE_ASPEED_I2C); object_property_add_child(obj, "i2c", OBJECT(&s->i2c), NULL); qdev_set_parent_bus(DEVICE(&s->i2c), sysbus_get_default()); object_initialize(&s->scu, sizeof(s->scu), TYPE_ASPEED_SCU); object_property_add_child(obj, "scu", OBJECT(&s->scu), NULL); qdev_set_parent_bus(DEVICE(&s->scu), sysbus_get_default()); qdev_prop_set_uint32(DEVICE(&s->scu), "silicon-rev", AST2400_A0_SILICON_REV); object_property_add_alias(obj, "hw-strap1", OBJECT(&s->scu), "hw-strap1", &error_abort); object_property_add_alias(obj, "hw-strap2", OBJECT(&s->scu), "hw-strap2", &error_abort); object_initialize(&s->smc, sizeof(s->smc), "aspeed.smc.fmc"); object_property_add_child(obj, "smc", OBJECT(&s->smc), NULL); qdev_set_parent_bus(DEVICE(&s->smc), sysbus_get_default()); object_initialize(&s->spi, sizeof(s->spi), "aspeed.smc.spi"); object_property_add_child(obj, "spi", OBJECT(&s->spi), NULL); qdev_set_parent_bus(DEVICE(&s->spi), sysbus_get_default()); }
static void bcm2835_peripherals_init(Object *obj) { BCM2835PeripheralState *s = BCM2835_PERIPHERALS(obj); /* Memory region for peripheral devices, which we export to our parent */ memory_region_init(&s->peri_mr, obj,"bcm2835-peripherals", 0x1000000); object_property_add_child(obj, "peripheral-io", OBJECT(&s->peri_mr), NULL); sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->peri_mr); /* Internal memory region for peripheral bus addresses (not exported) */ memory_region_init(&s->gpu_bus_mr, obj, "bcm2835-gpu", (uint64_t)1 << 32); object_property_add_child(obj, "gpu-bus", OBJECT(&s->gpu_bus_mr), NULL); /* Internal memory region for request/response communication with * mailbox-addressable peripherals (not exported) */ memory_region_init(&s->mbox_mr, obj, "bcm2835-mbox", MBOX_CHAN_COUNT << MBOX_AS_CHAN_SHIFT); /* Interrupt Controller */ object_initialize(&s->ic, sizeof(s->ic), TYPE_BCM2835_IC); object_property_add_child(obj, "ic", OBJECT(&s->ic), NULL); qdev_set_parent_bus(DEVICE(&s->ic), sysbus_get_default()); /* UART0 */ s->uart0 = SYS_BUS_DEVICE(object_new("pl011")); object_property_add_child(obj, "uart0", OBJECT(s->uart0), NULL); qdev_set_parent_bus(DEVICE(s->uart0), sysbus_get_default()); /* AUX / UART1 */ object_initialize(&s->aux, sizeof(s->aux), TYPE_BCM2835_AUX); object_property_add_child(obj, "aux", OBJECT(&s->aux), NULL); qdev_set_parent_bus(DEVICE(&s->aux), sysbus_get_default()); /* Mailboxes */ object_initialize(&s->mboxes, sizeof(s->mboxes), TYPE_BCM2835_MBOX); object_property_add_child(obj, "mbox", OBJECT(&s->mboxes), NULL); qdev_set_parent_bus(DEVICE(&s->mboxes), sysbus_get_default()); object_property_add_const_link(OBJECT(&s->mboxes), "mbox-mr", OBJECT(&s->mbox_mr), &error_abort); /* Framebuffer */ object_initialize(&s->fb, sizeof(s->fb), TYPE_BCM2835_FB); object_property_add_child(obj, "fb", OBJECT(&s->fb), NULL); object_property_add_alias(obj, "vcram-size", OBJECT(&s->fb), "vcram-size", &error_abort); qdev_set_parent_bus(DEVICE(&s->fb), sysbus_get_default()); object_property_add_const_link(OBJECT(&s->fb), "dma-mr", OBJECT(&s->gpu_bus_mr), &error_abort); /* Property channel */ object_initialize(&s->property, sizeof(s->property), TYPE_BCM2835_PROPERTY); object_property_add_child(obj, "property", OBJECT(&s->property), NULL); object_property_add_alias(obj, "board-rev", OBJECT(&s->property), "board-rev", &error_abort); qdev_set_parent_bus(DEVICE(&s->property), sysbus_get_default()); object_property_add_const_link(OBJECT(&s->property), "fb", OBJECT(&s->fb), &error_abort); object_property_add_const_link(OBJECT(&s->property), "dma-mr", OBJECT(&s->gpu_bus_mr), &error_abort); /* Random Number Generator */ object_initialize(&s->rng, sizeof(s->rng), TYPE_BCM2835_RNG); object_property_add_child(obj, "rng", OBJECT(&s->rng), NULL); qdev_set_parent_bus(DEVICE(&s->rng), sysbus_get_default()); /* Extended Mass Media Controller */ object_initialize(&s->sdhci, sizeof(s->sdhci), TYPE_SYSBUS_SDHCI); object_property_add_child(obj, "sdhci", OBJECT(&s->sdhci), NULL); qdev_set_parent_bus(DEVICE(&s->sdhci), sysbus_get_default()); /* SDHOST */ object_initialize(&s->sdhost, sizeof(s->sdhost), TYPE_BCM2835_SDHOST); object_property_add_child(obj, "sdhost", OBJECT(&s->sdhost), NULL); qdev_set_parent_bus(DEVICE(&s->sdhost), sysbus_get_default()); /* DMA Channels */ object_initialize(&s->dma, sizeof(s->dma), TYPE_BCM2835_DMA); object_property_add_child(obj, "dma", OBJECT(&s->dma), NULL); qdev_set_parent_bus(DEVICE(&s->dma), sysbus_get_default()); object_property_add_const_link(OBJECT(&s->dma), "dma-mr", OBJECT(&s->gpu_bus_mr), &error_abort); /* GPIO */ object_initialize(&s->gpio, sizeof(s->gpio), TYPE_BCM2835_GPIO); object_property_add_child(obj, "gpio", OBJECT(&s->gpio), NULL); qdev_set_parent_bus(DEVICE(&s->gpio), sysbus_get_default()); object_property_add_const_link(OBJECT(&s->gpio), "sdbus-sdhci", OBJECT(&s->sdhci.sdbus), &error_abort); object_property_add_const_link(OBJECT(&s->gpio), "sdbus-sdhost", OBJECT(&s->sdhost.sdbus), &error_abort); }
static void boston_mach_init(MachineState *machine) { DeviceState *dev; BostonState *s; Error *err = NULL; const char *cpu_model; MemoryRegion *flash, *ddr, *ddr_low_alias, *lcd, *platreg; MemoryRegion *sys_mem = get_system_memory(); XilinxPCIEHost *pcie2; PCIDevice *ahci; DriveInfo *hd[6]; Chardev *chr; int fw_size, fit_err; bool is_64b; if ((machine->ram_size % G_BYTE) || (machine->ram_size > (2 * G_BYTE))) { error_report("Memory size must be 1GB or 2GB"); exit(1); } cpu_model = machine->cpu_model ?: "I6400"; dev = qdev_create(NULL, TYPE_MIPS_BOSTON); qdev_init_nofail(dev); s = BOSTON(dev); s->mach = machine; s->cps = g_new0(MIPSCPSState, 1); if (!cpu_supports_cps_smp(cpu_model)) { error_report("Boston requires CPUs which support CPS"); exit(1); } is_64b = cpu_supports_isa(cpu_model, ISA_MIPS64); object_initialize(s->cps, sizeof(MIPSCPSState), TYPE_MIPS_CPS); qdev_set_parent_bus(DEVICE(s->cps), sysbus_get_default()); object_property_set_str(OBJECT(s->cps), cpu_model, "cpu-model", &err); object_property_set_int(OBJECT(s->cps), smp_cpus, "num-vp", &err); object_property_set_bool(OBJECT(s->cps), true, "realized", &err); if (err != NULL) { error_report("%s", error_get_pretty(err)); exit(1); } sysbus_mmio_map_overlap(SYS_BUS_DEVICE(s->cps), 0, 0, 1); flash = g_new(MemoryRegion, 1); memory_region_init_rom_device(flash, NULL, &boston_flash_ops, s, "boston.flash", 128 * M_BYTE, &err); memory_region_add_subregion_overlap(sys_mem, 0x18000000, flash, 0); ddr = g_new(MemoryRegion, 1); memory_region_allocate_system_memory(ddr, NULL, "boston.ddr", machine->ram_size); memory_region_add_subregion_overlap(sys_mem, 0x80000000, ddr, 0); ddr_low_alias = g_new(MemoryRegion, 1); memory_region_init_alias(ddr_low_alias, NULL, "boston_low.ddr", ddr, 0, MIN(machine->ram_size, (256 * M_BYTE))); memory_region_add_subregion_overlap(sys_mem, 0, ddr_low_alias, 0); xilinx_pcie_init(sys_mem, 0, 0x10000000, 32 * M_BYTE, 0x40000000, 1 * G_BYTE, get_cps_irq(s->cps, 2), false); xilinx_pcie_init(sys_mem, 1, 0x12000000, 32 * M_BYTE, 0x20000000, 512 * M_BYTE, get_cps_irq(s->cps, 1), false); pcie2 = xilinx_pcie_init(sys_mem, 2, 0x14000000, 32 * M_BYTE, 0x16000000, 1 * M_BYTE, get_cps_irq(s->cps, 0), true); platreg = g_new(MemoryRegion, 1); memory_region_init_io(platreg, NULL, &boston_platreg_ops, s, "boston-platregs", 0x1000); memory_region_add_subregion_overlap(sys_mem, 0x17ffd000, platreg, 0); if (!serial_hds[0]) { serial_hds[0] = qemu_chr_new("serial0", "null"); } s->uart = serial_mm_init(sys_mem, 0x17ffe000, 2, get_cps_irq(s->cps, 3), 10000000, serial_hds[0], DEVICE_NATIVE_ENDIAN); lcd = g_new(MemoryRegion, 1); memory_region_init_io(lcd, NULL, &boston_lcd_ops, s, "boston-lcd", 0x8); memory_region_add_subregion_overlap(sys_mem, 0x17fff000, lcd, 0); chr = qemu_chr_new("lcd", "vc:320x240"); qemu_chr_fe_init(&s->lcd_display, chr, NULL); qemu_chr_fe_set_handlers(&s->lcd_display, NULL, NULL, boston_lcd_event, s, NULL, true); ahci = pci_create_simple_multifunction(&PCI_BRIDGE(&pcie2->root)->sec_bus, PCI_DEVFN(0, 0), true, TYPE_ICH9_AHCI); g_assert(ARRAY_SIZE(hd) == ICH_AHCI(ahci)->ahci.ports); ide_drive_get(hd, ICH_AHCI(ahci)->ahci.ports); ahci_ide_create_devs(ahci, hd); if (machine->firmware) { fw_size = load_image_targphys(machine->firmware, 0x1fc00000, 4 * M_BYTE); if (fw_size == -1) { error_printf("unable to load firmware image '%s'\n", machine->firmware); exit(1); } } else if (machine->kernel_filename) { fit_err = load_fit(&boston_fit_loader, machine->kernel_filename, s); if (fit_err) { error_printf("unable to load FIT image\n"); exit(1); } gen_firmware(memory_region_get_ram_ptr(flash) + 0x7c00000, s->kernel_entry, s->fdt_base, is_64b); } else if (!qtest_enabled()) { error_printf("Please provide either a -kernel or -bios argument\n"); exit(1); } }
static void mps2_common_init(MachineState *machine) { MPS2MachineState *mms = MPS2_MACHINE(machine); MPS2MachineClass *mmc = MPS2_MACHINE_GET_CLASS(machine); MemoryRegion *system_memory = get_system_memory(); MachineClass *mc = MACHINE_GET_CLASS(machine); DeviceState *armv7m, *sccdev; if (strcmp(machine->cpu_type, mc->default_cpu_type) != 0) { error_report("This board can only be used with CPU %s", mc->default_cpu_type); exit(1); } /* The FPGA images have an odd combination of different RAMs, * because in hardware they are different implementations and * connected to different buses, giving varying performance/size * tradeoffs. For QEMU they're all just RAM, though. We arbitrarily * call the 16MB our "system memory", as it's the largest lump. * * Common to both boards: * 0x21000000..0x21ffffff : PSRAM (16MB) * AN385 only: * 0x00000000 .. 0x003fffff : ZBT SSRAM1 * 0x00400000 .. 0x007fffff : mirror of ZBT SSRAM1 * 0x20000000 .. 0x203fffff : ZBT SSRAM 2&3 * 0x20400000 .. 0x207fffff : mirror of ZBT SSRAM 2&3 * 0x01000000 .. 0x01003fff : block RAM (16K) * 0x01004000 .. 0x01007fff : mirror of above * 0x01008000 .. 0x0100bfff : mirror of above * 0x0100c000 .. 0x0100ffff : mirror of above * AN511 only: * 0x00000000 .. 0x0003ffff : FPGA block RAM * 0x00400000 .. 0x007fffff : ZBT SSRAM1 * 0x20000000 .. 0x2001ffff : SRAM * 0x20400000 .. 0x207fffff : ZBT SSRAM 2&3 * * The AN385 has a feature where the lowest 16K can be mapped * either to the bottom of the ZBT SSRAM1 or to the block RAM. * This is of no use for QEMU so we don't implement it (as if * zbt_boot_ctrl is always zero). */ memory_region_allocate_system_memory(&mms->psram, NULL, "mps.ram", 0x1000000); memory_region_add_subregion(system_memory, 0x21000000, &mms->psram); switch (mmc->fpga_type) { case FPGA_AN385: make_ram(&mms->ssram1, "mps.ssram1", 0x0, 0x400000); make_ram_alias(&mms->ssram1_m, "mps.ssram1_m", &mms->ssram1, 0x400000); make_ram(&mms->ssram23, "mps.ssram23", 0x20000000, 0x400000); make_ram_alias(&mms->ssram23_m, "mps.ssram23_m", &mms->ssram23, 0x20400000); make_ram(&mms->blockram, "mps.blockram", 0x01000000, 0x4000); make_ram_alias(&mms->blockram_m1, "mps.blockram_m1", &mms->blockram, 0x01004000); make_ram_alias(&mms->blockram_m2, "mps.blockram_m2", &mms->blockram, 0x01008000); make_ram_alias(&mms->blockram_m3, "mps.blockram_m3", &mms->blockram, 0x0100c000); break; case FPGA_AN511: make_ram(&mms->blockram, "mps.blockram", 0x0, 0x40000); make_ram(&mms->ssram1, "mps.ssram1", 0x00400000, 0x00800000); make_ram(&mms->sram, "mps.sram", 0x20000000, 0x20000); make_ram(&mms->ssram23, "mps.ssram23", 0x20400000, 0x400000); break; default: g_assert_not_reached(); } object_initialize(&mms->armv7m, sizeof(mms->armv7m), TYPE_ARMV7M); armv7m = DEVICE(&mms->armv7m); qdev_set_parent_bus(armv7m, sysbus_get_default()); switch (mmc->fpga_type) { case FPGA_AN385: qdev_prop_set_uint32(armv7m, "num-irq", 32); break; case FPGA_AN511: qdev_prop_set_uint32(armv7m, "num-irq", 64); break; default: g_assert_not_reached(); } qdev_prop_set_string(armv7m, "cpu-type", machine->cpu_type); object_property_set_link(OBJECT(&mms->armv7m), OBJECT(system_memory), "memory", &error_abort); object_property_set_bool(OBJECT(&mms->armv7m), true, "realized", &error_fatal); create_unimplemented_device("zbtsmram mirror", 0x00400000, 0x00400000); create_unimplemented_device("RESERVED 1", 0x00800000, 0x00800000); create_unimplemented_device("Block RAM", 0x01000000, 0x00010000); create_unimplemented_device("RESERVED 2", 0x01010000, 0x1EFF0000); create_unimplemented_device("RESERVED 3", 0x20800000, 0x00800000); create_unimplemented_device("PSRAM", 0x21000000, 0x01000000); /* These three ranges all cover multiple devices; we may implement * some of them below (in which case the real device takes precedence * over the unimplemented-region mapping). */ create_unimplemented_device("CMSDK APB peripheral region @0x40000000", 0x40000000, 0x00010000); create_unimplemented_device("CMSDK peripheral region @0x40010000", 0x40010000, 0x00010000); create_unimplemented_device("Extra peripheral region @0x40020000", 0x40020000, 0x00010000); create_unimplemented_device("RESERVED 4", 0x40030000, 0x001D0000); create_unimplemented_device("VGA", 0x41000000, 0x0200000); switch (mmc->fpga_type) { case FPGA_AN385: { /* The overflow IRQs for UARTs 0, 1 and 2 are ORed together. * Overflow for UARTs 4 and 5 doesn't trigger any interrupt. */ Object *orgate; DeviceState *orgate_dev; int i; orgate = object_new(TYPE_OR_IRQ); object_property_set_int(orgate, 6, "num-lines", &error_fatal); object_property_set_bool(orgate, true, "realized", &error_fatal); orgate_dev = DEVICE(orgate); qdev_connect_gpio_out(orgate_dev, 0, qdev_get_gpio_in(armv7m, 12)); for (i = 0; i < 5; i++) { static const hwaddr uartbase[] = {0x40004000, 0x40005000, 0x40006000, 0x40007000, 0x40009000}; Chardev *uartchr = i < MAX_SERIAL_PORTS ? serial_hds[i] : NULL; /* RX irq number; TX irq is always one greater */ static const int uartirq[] = {0, 2, 4, 18, 20}; qemu_irq txovrint = NULL, rxovrint = NULL; if (i < 3) { txovrint = qdev_get_gpio_in(orgate_dev, i * 2); rxovrint = qdev_get_gpio_in(orgate_dev, i * 2 + 1); } cmsdk_apb_uart_create(uartbase[i], qdev_get_gpio_in(armv7m, uartirq[i] + 1), qdev_get_gpio_in(armv7m, uartirq[i]), txovrint, rxovrint, NULL, uartchr, SYSCLK_FRQ); } break; } case FPGA_AN511: { /* The overflow IRQs for all UARTs are ORed together. * Tx and Rx IRQs for each UART are ORed together. */ Object *orgate; DeviceState *orgate_dev; int i; orgate = object_new(TYPE_OR_IRQ); object_property_set_int(orgate, 10, "num-lines", &error_fatal); object_property_set_bool(orgate, true, "realized", &error_fatal); orgate_dev = DEVICE(orgate); qdev_connect_gpio_out(orgate_dev, 0, qdev_get_gpio_in(armv7m, 12)); for (i = 0; i < 5; i++) { /* system irq numbers for the combined tx/rx for each UART */ static const int uart_txrx_irqno[] = {0, 2, 45, 46, 56}; static const hwaddr uartbase[] = {0x40004000, 0x40005000, 0x4002c000, 0x4002d000, 0x4002e000}; Chardev *uartchr = i < MAX_SERIAL_PORTS ? serial_hds[i] : NULL; Object *txrx_orgate; DeviceState *txrx_orgate_dev; txrx_orgate = object_new(TYPE_OR_IRQ); object_property_set_int(txrx_orgate, 2, "num-lines", &error_fatal); object_property_set_bool(txrx_orgate, true, "realized", &error_fatal); txrx_orgate_dev = DEVICE(txrx_orgate); qdev_connect_gpio_out(txrx_orgate_dev, 0, qdev_get_gpio_in(armv7m, uart_txrx_irqno[i])); cmsdk_apb_uart_create(uartbase[i], qdev_get_gpio_in(txrx_orgate_dev, 0), qdev_get_gpio_in(txrx_orgate_dev, 1), qdev_get_gpio_in(orgate_dev, i * 2), qdev_get_gpio_in(orgate_dev, i * 2 + 1), NULL, uartchr, SYSCLK_FRQ); } break; } default: g_assert_not_reached(); } cmsdk_apb_timer_create(0x40000000, qdev_get_gpio_in(armv7m, 8), SYSCLK_FRQ); cmsdk_apb_timer_create(0x40001000, qdev_get_gpio_in(armv7m, 9), SYSCLK_FRQ); object_initialize(&mms->scc, sizeof(mms->scc), TYPE_MPS2_SCC); sccdev = DEVICE(&mms->scc); qdev_set_parent_bus(sccdev, sysbus_get_default()); qdev_prop_set_uint32(sccdev, "scc-cfg4", 0x2); qdev_prop_set_uint32(sccdev, "scc-aid", 0x02000008); qdev_prop_set_uint32(sccdev, "scc-id", mmc->scc_id); object_property_set_bool(OBJECT(&mms->scc), true, "realized", &error_fatal); sysbus_mmio_map(SYS_BUS_DEVICE(sccdev), 0, 0x4002f000); /* In hardware this is a LAN9220; the LAN9118 is software compatible * except that it doesn't support the checksum-offload feature. */ lan9118_init(&nd_table[0], 0x40200000, qdev_get_gpio_in(armv7m, mmc->fpga_type == FPGA_AN385 ? 13 : 47)); system_clock_scale = NANOSECONDS_PER_SECOND / SYSCLK_FRQ; armv7m_load_kernel(ARM_CPU(first_cpu), machine->kernel_filename, 0x400000); }
static void aspeed_soc_init(Object *obj) { AspeedSoCState *s = ASPEED_SOC(obj); AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); int i; object_initialize(&s->cpu, sizeof(s->cpu), sc->info->cpu_type); object_property_add_child(obj, "cpu", OBJECT(&s->cpu), NULL); object_initialize(&s->scu, sizeof(s->scu), TYPE_ASPEED_SCU); object_property_add_child(obj, "scu", OBJECT(&s->scu), NULL); qdev_set_parent_bus(DEVICE(&s->scu), sysbus_get_default()); qdev_prop_set_uint32(DEVICE(&s->scu), "silicon-rev", sc->info->silicon_rev); object_property_add_alias(obj, "hw-strap1", OBJECT(&s->scu), "hw-strap1", &error_abort); object_property_add_alias(obj, "hw-strap2", OBJECT(&s->scu), "hw-strap2", &error_abort); object_property_add_alias(obj, "hw-prot-key", OBJECT(&s->scu), "hw-prot-key", &error_abort); object_initialize(&s->vic, sizeof(s->vic), TYPE_ASPEED_VIC); object_property_add_child(obj, "vic", OBJECT(&s->vic), NULL); qdev_set_parent_bus(DEVICE(&s->vic), sysbus_get_default()); object_initialize(&s->timerctrl, sizeof(s->timerctrl), TYPE_ASPEED_TIMER); object_property_add_child(obj, "timerctrl", OBJECT(&s->timerctrl), NULL); object_property_add_const_link(OBJECT(&s->timerctrl), "scu", OBJECT(&s->scu), &error_abort); qdev_set_parent_bus(DEVICE(&s->timerctrl), sysbus_get_default()); object_initialize(&s->i2c, sizeof(s->i2c), TYPE_ASPEED_I2C); object_property_add_child(obj, "i2c", OBJECT(&s->i2c), NULL); qdev_set_parent_bus(DEVICE(&s->i2c), sysbus_get_default()); object_initialize(&s->fmc, sizeof(s->fmc), sc->info->fmc_typename); object_property_add_child(obj, "fmc", OBJECT(&s->fmc), NULL); qdev_set_parent_bus(DEVICE(&s->fmc), sysbus_get_default()); object_property_add_alias(obj, "num-cs", OBJECT(&s->fmc), "num-cs", &error_abort); for (i = 0; i < sc->info->spis_num; i++) { object_initialize(&s->spi[i], sizeof(s->spi[i]), sc->info->spi_typename[i]); object_property_add_child(obj, "spi[*]", OBJECT(&s->spi[i]), NULL); qdev_set_parent_bus(DEVICE(&s->spi[i]), sysbus_get_default()); } object_initialize(&s->sdmc, sizeof(s->sdmc), TYPE_ASPEED_SDMC); object_property_add_child(obj, "sdmc", OBJECT(&s->sdmc), NULL); qdev_set_parent_bus(DEVICE(&s->sdmc), sysbus_get_default()); qdev_prop_set_uint32(DEVICE(&s->sdmc), "silicon-rev", sc->info->silicon_rev); object_property_add_alias(obj, "ram-size", OBJECT(&s->sdmc), "ram-size", &error_abort); object_property_add_alias(obj, "max-ram-size", OBJECT(&s->sdmc), "max-ram-size", &error_abort); for (i = 0; i < sc->info->wdts_num; i++) { object_initialize(&s->wdt[i], sizeof(s->wdt[i]), TYPE_ASPEED_WDT); object_property_add_child(obj, "wdt[*]", OBJECT(&s->wdt[i]), NULL); qdev_set_parent_bus(DEVICE(&s->wdt[i]), sysbus_get_default()); qdev_prop_set_uint32(DEVICE(&s->wdt[i]), "silicon-rev", sc->info->silicon_rev); } object_initialize(&s->ftgmac100, sizeof(s->ftgmac100), TYPE_FTGMAC100); object_property_add_child(obj, "ftgmac100", OBJECT(&s->ftgmac100), NULL); qdev_set_parent_bus(DEVICE(&s->ftgmac100), sysbus_get_default()); }
static void mips_cps_realize(DeviceState *dev, Error **errp) { MIPSCPSState *s = MIPS_CPS(dev); CPUMIPSState *env; MIPSCPU *cpu; int i; Error *err = NULL; target_ulong gcr_base; bool itu_present = false; bool saar_present = false; for (i = 0; i < s->num_vp; i++) { cpu = MIPS_CPU(cpu_create(s->cpu_type)); /* Init internal devices */ cpu_mips_irq_init_cpu(cpu); cpu_mips_clock_init(cpu); env = &cpu->env; if (cpu_mips_itu_supported(env)) { itu_present = true; /* Attach ITC Tag to the VP */ env->itc_tag = mips_itu_get_tag_region(&s->itu); env->itu = &s->itu; } qemu_register_reset(main_cpu_reset, cpu); } cpu = MIPS_CPU(first_cpu); env = &cpu->env; saar_present = (bool)env->saarp; /* Inter-Thread Communication Unit */ if (itu_present) { object_initialize(&s->itu, sizeof(s->itu), TYPE_MIPS_ITU); qdev_set_parent_bus(DEVICE(&s->itu), sysbus_get_default()); object_property_set_int(OBJECT(&s->itu), 16, "num-fifo", &err); object_property_set_int(OBJECT(&s->itu), 16, "num-semaphores", &err); object_property_set_bool(OBJECT(&s->itu), saar_present, "saar-present", &err); if (saar_present) { qdev_prop_set_ptr(DEVICE(&s->itu), "saar", (void *)&env->CP0_SAAR); } object_property_set_bool(OBJECT(&s->itu), true, "realized", &err); if (err != NULL) { error_propagate(errp, err); return; } memory_region_add_subregion(&s->container, 0, sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->itu), 0)); } /* Cluster Power Controller */ object_initialize(&s->cpc, sizeof(s->cpc), TYPE_MIPS_CPC); qdev_set_parent_bus(DEVICE(&s->cpc), sysbus_get_default()); object_property_set_int(OBJECT(&s->cpc), s->num_vp, "num-vp", &err); object_property_set_int(OBJECT(&s->cpc), 1, "vp-start-running", &err); object_property_set_bool(OBJECT(&s->cpc), true, "realized", &err); if (err != NULL) { error_propagate(errp, err); return; } memory_region_add_subregion(&s->container, 0, sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->cpc), 0)); /* Global Interrupt Controller */ object_initialize(&s->gic, sizeof(s->gic), TYPE_MIPS_GIC); qdev_set_parent_bus(DEVICE(&s->gic), sysbus_get_default()); object_property_set_int(OBJECT(&s->gic), s->num_vp, "num-vp", &err); object_property_set_int(OBJECT(&s->gic), 128, "num-irq", &err); object_property_set_bool(OBJECT(&s->gic), true, "realized", &err); if (err != NULL) { error_propagate(errp, err); return; } memory_region_add_subregion(&s->container, 0, sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->gic), 0)); /* Global Configuration Registers */ gcr_base = env->CP0_CMGCRBase << 4; object_initialize(&s->gcr, sizeof(s->gcr), TYPE_MIPS_GCR); qdev_set_parent_bus(DEVICE(&s->gcr), sysbus_get_default()); object_property_set_int(OBJECT(&s->gcr), s->num_vp, "num-vp", &err); object_property_set_int(OBJECT(&s->gcr), 0x800, "gcr-rev", &err); object_property_set_int(OBJECT(&s->gcr), gcr_base, "gcr-base", &err); object_property_set_link(OBJECT(&s->gcr), OBJECT(&s->gic.mr), "gic", &err); object_property_set_link(OBJECT(&s->gcr), OBJECT(&s->cpc.mr), "cpc", &err); object_property_set_bool(OBJECT(&s->gcr), true, "realized", &err); if (err != NULL) { error_propagate(errp, err); return; } memory_region_add_subregion(&s->container, gcr_base, sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->gcr), 0)); }
static void fsl_imx6_init(Object *obj) { FslIMX6State *s = FSL_IMX6(obj); char name[NAME_SIZE]; int i; if (smp_cpus > FSL_IMX6_NUM_CPUS) { error_report("%s: Only %d CPUs are supported (%d requested)", TYPE_FSL_IMX6, FSL_IMX6_NUM_CPUS, smp_cpus); exit(1); } for (i = 0; i < smp_cpus; i++) { object_initialize(&s->cpu[i], sizeof(s->cpu[i]), "cortex-a9-" TYPE_ARM_CPU); snprintf(name, NAME_SIZE, "cpu%d", i); object_property_add_child(obj, name, OBJECT(&s->cpu[i]), NULL); } object_initialize(&s->a9mpcore, sizeof(s->a9mpcore), TYPE_A9MPCORE_PRIV); qdev_set_parent_bus(DEVICE(&s->a9mpcore), sysbus_get_default()); object_property_add_child(obj, "a9mpcore", OBJECT(&s->a9mpcore), NULL); object_initialize(&s->ccm, sizeof(s->ccm), TYPE_IMX6_CCM); qdev_set_parent_bus(DEVICE(&s->ccm), sysbus_get_default()); object_property_add_child(obj, "ccm", OBJECT(&s->ccm), NULL); object_initialize(&s->src, sizeof(s->src), TYPE_IMX6_SRC); qdev_set_parent_bus(DEVICE(&s->src), sysbus_get_default()); object_property_add_child(obj, "src", OBJECT(&s->src), NULL); for (i = 0; i < FSL_IMX6_NUM_UARTS; i++) { object_initialize(&s->uart[i], sizeof(s->uart[i]), TYPE_IMX_SERIAL); qdev_set_parent_bus(DEVICE(&s->uart[i]), sysbus_get_default()); snprintf(name, NAME_SIZE, "uart%d", i + 1); object_property_add_child(obj, name, OBJECT(&s->uart[i]), NULL); } object_initialize(&s->gpt, sizeof(s->gpt), TYPE_IMX6_GPT); qdev_set_parent_bus(DEVICE(&s->gpt), sysbus_get_default()); object_property_add_child(obj, "gpt", OBJECT(&s->gpt), NULL); for (i = 0; i < FSL_IMX6_NUM_EPITS; i++) { object_initialize(&s->epit[i], sizeof(s->epit[i]), TYPE_IMX_EPIT); qdev_set_parent_bus(DEVICE(&s->epit[i]), sysbus_get_default()); snprintf(name, NAME_SIZE, "epit%d", i + 1); object_property_add_child(obj, name, OBJECT(&s->epit[i]), NULL); } for (i = 0; i < FSL_IMX6_NUM_I2CS; i++) { object_initialize(&s->i2c[i], sizeof(s->i2c[i]), TYPE_IMX_I2C); qdev_set_parent_bus(DEVICE(&s->i2c[i]), sysbus_get_default()); snprintf(name, NAME_SIZE, "i2c%d", i + 1); object_property_add_child(obj, name, OBJECT(&s->i2c[i]), NULL); } for (i = 0; i < FSL_IMX6_NUM_GPIOS; i++) { object_initialize(&s->gpio[i], sizeof(s->gpio[i]), TYPE_IMX_GPIO); qdev_set_parent_bus(DEVICE(&s->gpio[i]), sysbus_get_default()); snprintf(name, NAME_SIZE, "gpio%d", i + 1); object_property_add_child(obj, name, OBJECT(&s->gpio[i]), NULL); } for (i = 0; i < FSL_IMX6_NUM_ESDHCS; i++) { object_initialize(&s->esdhc[i], sizeof(s->esdhc[i]), TYPE_IMX_USDHC); qdev_set_parent_bus(DEVICE(&s->esdhc[i]), sysbus_get_default()); snprintf(name, NAME_SIZE, "sdhc%d", i + 1); object_property_add_child(obj, name, OBJECT(&s->esdhc[i]), NULL); } for (i = 0; i < FSL_IMX6_NUM_ECSPIS; i++) { object_initialize(&s->spi[i], sizeof(s->spi[i]), TYPE_IMX_SPI); qdev_set_parent_bus(DEVICE(&s->spi[i]), sysbus_get_default()); snprintf(name, NAME_SIZE, "spi%d", i + 1); object_property_add_child(obj, name, OBJECT(&s->spi[i]), NULL); } object_initialize(&s->eth, sizeof(s->eth), TYPE_IMX_ENET); qdev_set_parent_bus(DEVICE(&s->eth), sysbus_get_default()); object_property_add_child(obj, "eth", OBJECT(&s->eth), NULL); }