bool timer_set(long cycles, bool start)
{
unsigned int divider = cycles, prescaler_bit = 0, prescaler = 1, old_irq;
if(cycles < 1)
return false;
if(start && pfn_unregister != NULL)
{
pfn_unregister();
pfn_unregister = NULL;
}
/* Increase prescale values starting from 0 to make the cycle count fit */
while(divider > 65535 && prescaler <= 1024)
{
prescaler <<= 2; /* 1, 4, 16, 64, 256, 1024 */
prescaler_bit++;
divider = cycles / prescaler;
}
old_irq = disable_irq_save();
__tcu_stop_counter(1);
if(start)
{
__tcu_disable_pwm_output(1);
__tcu_mask_half_match_irq(1);
__tcu_unmask_full_match_irq(1);
/* EXTAL clock = CFG_EXTAL (12Mhz in most targets) */
__tcu_select_extalclk(1);
}
REG_TCU_TCSR(1) = (REG_TCU_TCSR(1) & ~TCU_TCSR_PRESCALE_MASK) | (prescaler_bit << TCU_TCSR_PRESCALE_BIT);
REG_TCU_TCNT(1) = 0;
REG_TCU_TDHR(1) = 0;
REG_TCU_TDFR(1) = divider;
__tcu_clear_full_match_flag(1);
if(start)
{
system_enable_irq(IRQ_TCU1);
__tcu_start_counter(1);
}
restore_irq(old_irq);
return true;
}
void adc_init(void)
{
__cpm_start_sadc();
REG_SADC_ENA = 0;
REG_SADC_STATE &= ~REG_SADC_STATE;
REG_SADC_CTRL = 0x1F;
REG_SADC_CFG = SADC_CFG_INIT;
system_enable_irq(IRQ_SADC);
REG_SADC_SAMETIME = 10;
REG_SADC_WAITTIME = 100;
REG_SADC_STATE &= ~REG_SADC_STATE;
REG_SADC_CTRL = ~SADC_CTRL_PBATRDYM;
REG_SADC_ENA = 0;
mutex_init(&battery_mtx);
}
