void app_cpu_load_init(void)
{
/* Reset counters */
app_cpu_load_time_active = 0;
app_cpu_load_time_sleep = 0;
/* Start Timer counter used to monitor CPU timing */
tc45_enable(&TCC4);
tc45_write_clock_source(&TCC4, TC45_CLKSEL_DIV256_gc); /* 24MHz / 256 */
tc45_set_direction(&TCC4, TC45_UP);
/* Display static background */
gfx_mono_draw_string(DISPLAY_CPU_LOAD_TEXT,
DISPLAY_CPU_LOAD_TEXT_POS_X,
DISPLAY_CPU_LOAD_TEXT_POS_Y,
&sysfont);
gfx_mono_draw_filled_rect(
DISPLAY_CPU_LOAD_PROBAR_START_POS_X,
DISPLAY_CPU_LOAD_PROBAR_START_POS_Y,
DISPLAY_CPU_LOAD_PROBAR_START_SIZE_X,
DISPLAY_CPU_LOAD_PROBAR_START_SIZE_Y,
GFX_PIXEL_SET);
gfx_mono_draw_filled_rect(
DISPLAY_CPU_LOAD_PROBAR_STOP_POS_X,
DISPLAY_CPU_LOAD_PROBAR_STOP_POS_Y,
DISPLAY_CPU_LOAD_PROBAR_STOP_SIZE_X,
DISPLAY_CPU_LOAD_PROBAR_STOP_SIZE_Y,
GFX_PIXEL_SET);
}
/**
* \brief Test read from fixed location, trigger from timer and callback
*
* \note This test sets up a timer to trigger the EDMA module,
* which in turn reads the timer45_overflow_counter variable and writes
* it to memory sequentially. It then checks to see that the memory block
* written is sequential according to the overflow count. This test uses the
* event system wired on timer45 overflow as trigger.
*
* \param test Current test
*/
static void run_edma_triggered_with_callback(const struct test_case *test)
{
struct edma_channel_config config_params;
bool success;
/* Null the buffer */
set_buffer(dest_block_tc45, 0x0000);
/* Null out the config parameter struct */
memset(&config_params, 0, sizeof(config_params));
/* Enable the Event System on EVSYS_CH_2 */
EVSYS.CH2MUX = EVSYS_CHMUX_TCC4_OVF_gc;
/*
* Enable the timer, and set it to count up.
* When it overflows, it triggers the EDMA to
* read timer45_overflow_counter.
*/
tc45_set_overflow_interrupt_callback(&TIMER45,
timer45_overflow_callback);
tc45_enable(&TIMER45);
tc45_set_overflow_interrupt_level(&TIMER45, TC45_INT_LVL_LO);
tc45_set_direction(&TIMER45, TC45_UP);
tc45_write_period(&TIMER45, TIMER45_PERIOD);
tc45_set_resolution(&TIMER45, TIMER45_RESOLUTION);
/*
* Enable the EDMA module, standard channel 0,
* peripheral channels 2 and 3
*/
edma_enable(EDMA_CHMODE_STD0_gc);
/* Set callback for transfer done */
edma_set_callback(EDMA_CH_0, ut_edma_transfer_is_complete);
/* Set low interrupt level */
edma_channel_set_interrupt_level(&config_params, EDMA_INT_LVL_LO);
/* Set up the EDMA to read the timer value
*
* - Single shot transfer mode
* - 1 byte (16-bit) burst length
* - Increment on source and destination
* - Reload on burst for source
* - No reload for destination
*/
edma_channel_set_single_shot(&config_params);
edma_channel_set_burst_length(&config_params,
EDMA_CH_BURSTLEN_1BYTE_gc);
edma_channel_set_src_reload_mode(&config_params,
EDMA_CH_RELOAD_BURST_gc);
edma_channel_set_src_dir_mode(&config_params, EDMA_CH_DIR_FIXED_gc);
edma_channel_set_dest_reload_mode(&config_params,
EDMA_CH_RELOAD_NONE_gc);
edma_channel_set_dest_dir_mode(&config_params, EDMA_CH_DESTDIR_INC_gc);
/* Set trigger source to Event Channel 2 (set to TCC4's overflow) */
edma_channel_set_trigger_source(&config_params,
EDMA_CH_TRIGSRC_EVSYS_CH2_gc);
/* Transfer DEST_BLOCK_TC45_SIZE bytes */
edma_channel_set_transfer_count16(&config_params, DEST_BLOCK_TC45_SIZE);
/* Set address */
edma_channel_set_source_address(&config_params,
(uint16_t)(uintptr_t)&timer45_overflow_counter);
edma_channel_set_destination_address(&config_params,
(uint16_t)(uintptr_t)dest_block_tc45);
/* Reset the channel */
edma_channel_reset(EDMA_CH_0);
/* Write the config */
edma_channel_write_config(EDMA_CH_0, &config_params);
/* Enable the channel */
edma_channel_enable(EDMA_CH_0);
/* Wait for transfer to finish */
while (!edma_has_completed) {
/* Intentionally left empty */
}
/* Disable EDMA and stop TC45 interrupts */
tc45_set_overflow_interrupt_level(&TIMER45, TC45_INT_LVL_OFF);
edma_disable();
/* Verify that the result is as expected */
success = block_compare(dest_block_tc45, expected_result_tc,
DEST_BLOCK_TC45_SIZE);
test_assert_true(test, success, "Result is not as expected");
/*
* Stop TIMER45:
* Already done in EDMA callback "ut_edma_transfer_is_complete()"
*/
}
