static void tegra_aic326x_shutdown(struct snd_pcm_substream *substream) { struct snd_soc_pcm_runtime *rtd = substream->private_data; struct snd_soc_dai *cpu_dai = rtd->cpu_dai; struct tegra30_i2s *i2s = snd_soc_dai_get_drvdata(cpu_dai); if (!i2s->is_dam_used) return; if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { tegra30_ahub_unset_rx_cif_source( TEGRA30_AHUB_RXCIF_I2S0_RX0 + i2s->id); tegra30_ahub_disable_clocks(); } else { if (!i2s->is_call_mode_rec) return; i2s->is_call_mode_rec = 0; /* disable the dams*/ tegra30_dam_enable(i2s->call_record_dam_ifc, TEGRA30_DAM_DISABLE, TEGRA30_DAM_CHIN1); tegra30_dam_enable(i2s->call_record_dam_ifc, TEGRA30_DAM_DISABLE, TEGRA30_DAM_CHIN0_SRC); tegra30_dam_enable(i2s->call_record_dam_ifc2, TEGRA30_DAM_DISABLE, TEGRA30_DAM_CHIN1); tegra30_dam_enable(i2s->call_record_dam_ifc2, TEGRA30_DAM_DISABLE, TEGRA30_DAM_CHIN0_SRC); /* disconnect the ahub connections*/ tegra30_ahub_unset_rx_cif_source(TEGRA30_AHUB_RXCIF_DAM0_RX0 + (i2s->call_record_dam_ifc2*2)); tegra30_ahub_unset_rx_cif_source(TEGRA30_AHUB_RXCIF_DAM0_RX1 + (i2s->call_record_dam_ifc2*2)); tegra30_ahub_unset_rx_cif_source(TEGRA30_AHUB_RXCIF_DAM0_RX0 + (i2s->call_record_dam_ifc*2)); tegra30_ahub_unset_rx_cif_source(i2s->rxcif); /* free the dam channels and dam controllers */ tegra30_dam_disable_clock(i2s->call_record_dam_ifc); tegra30_dam_free_channel(i2s->call_record_dam_ifc, TEGRA30_DAM_CHIN1); tegra30_dam_free_channel(i2s->call_record_dam_ifc, TEGRA30_DAM_CHIN0_SRC); tegra30_dam_free_controller(i2s->call_record_dam_ifc); tegra30_dam_disable_clock(i2s->call_record_dam_ifc2); tegra30_dam_free_channel(i2s->call_record_dam_ifc2, TEGRA30_DAM_CHIN1); tegra30_dam_free_channel(i2s->call_record_dam_ifc2, TEGRA30_DAM_CHIN0_SRC); tegra30_dam_free_controller(i2s->call_record_dam_ifc2); } return; }
static int tegra30_dam_runtime_suspend(struct device *dev) { struct tegra30_dam_context *dam = dev_get_drvdata(dev); tegra30_ahub_disable_clocks(); regcache_cache_only(dam->regmap, true); clk_disable_unprepare(dam->dam_clk); return 0; }
static void tegra_dmic_dai_shutdown(struct snd_pcm_substream *substream, struct snd_soc_dai *dai) { struct tegra_dmic *dmic = snd_soc_dai_get_drvdata(dai); mutex_lock(&dmic->mutex); /* Free up FIFOs and unset connection. */ tegra30_ahub_free_rx_fifo(dmic->rx_cif); tegra30_ahub_unset_rx_cif_source(TEGRA30_AHUB_RXCIF_APBIF_RX0); clk_disable(dmic->clk); tegra30_ahub_disable_clocks(); mutex_unlock(&dmic->mutex); }
int tegra30_ahub_set_rx_cif_stereo_conv(enum tegra30_ahub_rxcif rxcif) { int channel = rxcif - TEGRA30_AHUB_RXCIF_APBIF_RX0; unsigned int reg, val; tegra30_ahub_enable_clocks(); reg = TEGRA30_AHUB_CIF_RX_CTRL + (channel * TEGRA30_AHUB_CIF_RX_CTRL_STRIDE); val = tegra30_apbif_read(reg); val &= ~TEGRA30_AUDIOCIF_CTRL_STEREO_CONV_MASK; val |= TEGRA30_AUDIOCIF_CTRL_STEREO_CONV_AVG; tegra30_apbif_write(reg, val); tegra30_ahub_disable_clocks(); return 0; }
static int tegra30_dam_show(struct seq_file *s, void *unused) { #define REG(r) { r, #r } static const struct { int offset; const char *name; } regs[] = { REG(TEGRA30_DAM_CTRL), REG(TEGRA30_DAM_CLIP), REG(TEGRA30_DAM_CLIP_THRESHOLD), REG(TEGRA30_DAM_AUDIOCIF_OUT_CTRL), REG(TEGRA30_DAM_CH0_CTRL), REG(TEGRA30_DAM_CH0_CONV), REG(TEGRA30_DAM_AUDIOCIF_CH0_CTRL), REG(TEGRA30_DAM_CH1_CTRL), REG(TEGRA30_DAM_CH1_CONV), REG(TEGRA30_DAM_AUDIOCIF_CH1_CTRL), }; #undef REG struct tegra30_dam_context *dam = s->private; int i; tegra30_ahub_enable_clocks(); clk_enable(dam->dam_clk); for (i = 0; i < ARRAY_SIZE(regs); i++) { u32 val = tegra30_dam_readl(dam, regs[i].offset); seq_printf(s, "%s = %08x\n", regs[i].name, val); } clk_disable(dam->dam_clk); tegra30_ahub_disable_clocks(); return 0; }
static void tegra30_spdif_disable_clocks(struct tegra30_spdif *spdif) { tegra30_ahub_disable_clocks(); clk_disable(spdif->clk_spdif_out); }