예제 #1
0
파일: platsmp.c 프로젝트: Aqueti/kernels
static int tegra_boot_secondary(unsigned int cpu,
					  struct task_struct *idle)
{
	if (IS_ENABLED(CONFIG_ARCH_TEGRA_2x_SOC) && tegra_get_chip_id() == TEGRA20)
		return tegra20_boot_secondary(cpu, idle);
	if (IS_ENABLED(CONFIG_ARCH_TEGRA_3x_SOC) && tegra_get_chip_id() == TEGRA30)
		return tegra30_boot_secondary(cpu, idle);
	if (IS_ENABLED(CONFIG_ARCH_TEGRA_114_SOC) && tegra_get_chip_id() == TEGRA114)
		return tegra114_boot_secondary(cpu, idle);
	if (IS_ENABLED(CONFIG_ARCH_TEGRA_124_SOC) && tegra_get_chip_id() == TEGRA124)
		return tegra114_boot_secondary(cpu, idle);

	return -EINVAL;
}
예제 #2
0
파일: flowctrl.c 프로젝트: 0-T-0/ps4-linux
void flowctrl_cpu_suspend_exit(unsigned int cpuid)
{
	unsigned int reg;

	/* Disable powergating via flow controller for CPU0 */
	reg = flowctrl_read_cpu_csr(cpuid);
	switch (tegra_get_chip_id()) {
	case TEGRA20:
		/* clear wfe bitmap */
		reg &= ~TEGRA20_FLOW_CTRL_CSR_WFE_BITMAP;
		/* clear wfi bitmap */
		reg &= ~TEGRA20_FLOW_CTRL_CSR_WFI_BITMAP;
		break;
	case TEGRA30:
	case TEGRA114:
	case TEGRA124:
		/* clear wfe bitmap */
		reg &= ~TEGRA30_FLOW_CTRL_CSR_WFE_BITMAP;
		/* clear wfi bitmap */
		reg &= ~TEGRA30_FLOW_CTRL_CSR_WFI_BITMAP;
		break;
	}
	reg &= ~FLOW_CTRL_CSR_ENABLE;			/* clear enable */
	reg |= FLOW_CTRL_CSR_INTR_FLAG;			/* clear intr */
	reg |= FLOW_CTRL_CSR_EVENT_FLAG;		/* clear event */
	flowctrl_write_cpu_csr(cpuid, reg);
}
예제 #3
0
void tegra_cpuidle_pcie_irqs_in_use(void)
{
	switch (tegra_get_chip_id()) {
	case TEGRA20:
		if (IS_ENABLED(CONFIG_ARCH_TEGRA_2x_SOC))
			tegra20_cpuidle_pcie_irqs_in_use();
		break;
	}
}
예제 #4
0
static void __init legacy_fuse_init(void)
{
	switch (tegra_get_chip_id()) {
	case TEGRA30:
		fuse_info = &tegra30_info;
		break;
	case TEGRA114:
		fuse_info = &tegra114_info;
		break;
	case TEGRA124:
	case TEGRA132:
		fuse_info = &tegra124_info;
		break;
	default:
		return;
	}

	fuse_base = ioremap(TEGRA_FUSE_BASE, TEGRA_FUSE_SIZE);
}
예제 #5
0
void __init tegra_cpuidle_init(void)
{
	switch (tegra_get_chip_id()) {
	case TEGRA20:
		if (IS_ENABLED(CONFIG_ARCH_TEGRA_2x_SOC))
			tegra20_cpuidle_init();
		break;
	case TEGRA30:
		if (IS_ENABLED(CONFIG_ARCH_TEGRA_3x_SOC))
			tegra30_cpuidle_init();
		break;
	case TEGRA114:
	case TEGRA124:
		if (IS_ENABLED(CONFIG_ARCH_TEGRA_114_SOC) ||
		    IS_ENABLED(CONFIG_ARCH_TEGRA_124_SOC))
			tegra114_cpuidle_init();
		break;
	}
}
예제 #6
0
파일: flowctrl.c 프로젝트: 0-T-0/ps4-linux
void flowctrl_cpu_suspend_enter(unsigned int cpuid)
{
	unsigned int reg;
	int i;

	reg = flowctrl_read_cpu_csr(cpuid);
	switch (tegra_get_chip_id()) {
	case TEGRA20:
		/* clear wfe bitmap */
		reg &= ~TEGRA20_FLOW_CTRL_CSR_WFE_BITMAP;
		/* clear wfi bitmap */
		reg &= ~TEGRA20_FLOW_CTRL_CSR_WFI_BITMAP;
		/* pwr gating on wfe */
		reg |= TEGRA20_FLOW_CTRL_CSR_WFE_CPU0 << cpuid;
		break;
	case TEGRA30:
	case TEGRA114:
	case TEGRA124:
		/* clear wfe bitmap */
		reg &= ~TEGRA30_FLOW_CTRL_CSR_WFE_BITMAP;
		/* clear wfi bitmap */
		reg &= ~TEGRA30_FLOW_CTRL_CSR_WFI_BITMAP;
		/* pwr gating on wfi */
		reg |= TEGRA30_FLOW_CTRL_CSR_WFI_CPU0 << cpuid;
		break;
	}
	reg |= FLOW_CTRL_CSR_INTR_FLAG;			/* clear intr flag */
	reg |= FLOW_CTRL_CSR_EVENT_FLAG;		/* clear event flag */
	reg |= FLOW_CTRL_CSR_ENABLE;			/* pwr gating */
	flowctrl_write_cpu_csr(cpuid, reg);

	for (i = 0; i < num_possible_cpus(); i++) {
		if (i == cpuid)
			continue;
		reg = flowctrl_read_cpu_csr(i);
		reg |= FLOW_CTRL_CSR_EVENT_FLAG;
		reg |= FLOW_CTRL_CSR_INTR_FLAG;
		flowctrl_write_cpu_csr(i, reg);
	}
}
예제 #7
0
static void tegra_cpu_reset_handler_enable(void)
{
    void __iomem *iram_base = IO_ADDRESS(TEGRA_IRAM_BASE);
#if !defined(CONFIG_TEGRA_USE_SECURE_KERNEL)
    void __iomem *evp_cpu_reset =
        IO_ADDRESS(TEGRA_EXCEPTION_VECTORS_BASE + 0x100);
    void __iomem *sb_ctrl = IO_ADDRESS(TEGRA_SB_BASE);
    unsigned long reg;
#endif
    BUG_ON(is_enabled);
    BUG_ON(tegra_cpu_reset_handler_size > TEGRA_RESET_HANDLER_SIZE);

    memcpy(iram_base, (void *)__tegra_cpu_reset_handler_start,
           tegra_cpu_reset_handler_size);

#if defined(CONFIG_TEGRA_USE_SECURE_KERNEL)
    tegra_generic_smc(0x82000001,
                      TEGRA_RESET_HANDLER_BASE + tegra_cpu_reset_handler_offset, 0);
#else
    /* NOTE: This must be the one and only write to the EVP CPU reset
    	 vector in the entire system. */
    writel(TEGRA_RESET_HANDLER_BASE + tegra_cpu_reset_handler_offset,
           evp_cpu_reset);
    wmb();
    reg = readl(evp_cpu_reset);

    /*
     * Prevent further modifications to the physical reset vector.
     *  NOTE: Has no effect on chips prior to Tegra30.
     */
    if (tegra_get_chip_id() != TEGRA_CHIPID_TEGRA2) {
        reg = readl(sb_ctrl);
        reg |= 2;
        writel(reg, sb_ctrl);
        wmb();
    }
#endif
    is_enabled = true;
}
예제 #8
0
void __init tegra30_init_fuse_early(void)
{
	struct device_node *np;
	const struct of_device_id *of_match;

	np = of_find_matching_node_and_match(NULL, tegra30_fuse_of_match,
						&of_match);
	if (np) {
		fuse_base = of_iomap(np, 0);
		fuse_info = (struct tegra_fuse_info *)of_match->data;
	} else
		legacy_fuse_init();

	if (!fuse_base) {
		pr_warn("fuse DT node missing and unknown chip id: 0x%02x\n",
			tegra_get_chip_id());
		return;
	}

	tegra_init_revision();
	speedo_tbl[fuse_info->speedo_idx](&tegra_sku_info);
	tegra30_fuse_add_randomness();
}