/******************************************************************************* * Initialize the gic, configure the SCR. ******************************************************************************/ void bl31_platform_setup(void) { uint32_t tmp_reg; /* * Initialize delay timer */ tegra_delay_timer_init(); /* * Setup secondary CPU POR infrastructure. */ plat_secondary_setup(); /* * Initial Memory Controller configuration. */ tegra_memctrl_setup(); /* * Do initial security configuration to allow DRAM/device access. */ tegra_memctrl_tzdram_setup(tegra_bl31_phys_base, plat_bl31_params_from_bl2.tzdram_size); /* Set the next EL to be AArch64 */ tmp_reg = SCR_RES1_BITS | SCR_RW_BIT; write_scr(tmp_reg); /* Initialize the gic cpu and distributor interfaces */ tegra_gic_setup(); }
/******************************************************************************* * Handler called when a power domain has just been powered on after * being turned off earlier. The target_state encodes the low power state that * each level has woken up from. ******************************************************************************/ void tegra_pwr_domain_on_finish(const psci_power_state_t *target_state) { plat_params_from_bl2_t *plat_params; /* * Initialize the GIC cpu and distributor interfaces */ tegra_gic_setup(); /* * Check if we are exiting from deep sleep. */ if (target_state->pwr_domain_state[PLAT_MAX_PWR_LVL] == PSTATE_ID_SOC_POWERDN) { /* * Lock scratch registers which hold the CPU vectors. */ tegra_pmc_lock_cpu_vectors(); /* * SMMU configuration. */ tegra_memctrl_setup(); /* * Security configuration to allow DRAM/device access. */ plat_params = bl31_get_plat_params(); tegra_memctrl_tzdram_setup(tegra_bl31_phys_base, plat_params->tzdram_size); } /* * Reset hardware settings. */ tegra_soc_pwr_domain_on_finish(target_state); }
/******************************************************************************* * Initialize the GIC and SGIs ******************************************************************************/ void plat_gic_setup(void) { tegra_gic_setup(NULL, 0); }