void tegra_fiq_enable(int irq) { void __iomem *base = IO_ADDRESS(TEGRA_ARM_PERIF_BASE + 0x100); /* enable FIQ */ u32 val = readl(base + GIC_CPU_CTRL); val &= ~8; /* pass FIQs through */ val |= 2; /* enableNS */ writel(val, base + GIC_CPU_CTRL); tegra_legacy_select_fiq(irq, true); tegra_legacy_unmask_irq(irq); }
static void tegra_unmask(struct irq_data *d) { tegra_gic_unmask_irq(d); tegra_legacy_unmask_irq(d->irq); }