/******************************************************************************* * Initialize the gic, configure the SCR. ******************************************************************************/ void bl31_platform_setup(void) { uint32_t tmp_reg; /* * Initialize delay timer */ tegra_delay_timer_init(); /* * Setup secondary CPU POR infrastructure. */ plat_secondary_setup(); /* * Initial Memory Controller configuration. */ tegra_memctrl_setup(); /* * Do initial security configuration to allow DRAM/device access. */ tegra_memctrl_tzdram_setup(tegra_bl31_phys_base, plat_bl31_params_from_bl2.tzdram_size); /* Set the next EL to be AArch64 */ tmp_reg = SCR_RES1_BITS | SCR_RW_BIT; write_scr(tmp_reg); /* Initialize the gic cpu and distributor interfaces */ tegra_gic_setup(); }
/******************************************************************************* * Initialize the gic, configure the SCR. ******************************************************************************/ void bl31_platform_setup(void) { /* * Add timestamp for platform setup entry. */ boot_profiler_add_record("[TF] plat setup entry"); /* Initialize the gic cpu and distributor interfaces */ plat_gic_setup(); /* * Setup secondary CPU POR infrastructure. */ plat_secondary_setup(); /* * Initial Memory Controller configuration. */ tegra_memctrl_setup(); /* * Set up the TZRAM memory aperture to allow only secure world * access */ tegra_memctrl_tzram_setup(TEGRA_TZRAM_BASE, TEGRA_TZRAM_SIZE); /* * Late setup handler to allow platforms to performs additional * functionality. * This handler gets called with MMU enabled. */ plat_late_platform_setup(); /* * Add timestamp for platform setup exit. */ boot_profiler_add_record("[TF] plat setup exit"); INFO("BL3-1: Tegra platform setup complete\n"); }
/******************************************************************************* * Handler called when a power domain has just been powered on after * being turned off earlier. The target_state encodes the low power state that * each level has woken up from. ******************************************************************************/ void tegra_pwr_domain_on_finish(const psci_power_state_t *target_state) { plat_params_from_bl2_t *plat_params; /* * Initialize the GIC cpu and distributor interfaces */ tegra_gic_setup(); /* * Check if we are exiting from deep sleep. */ if (target_state->pwr_domain_state[PLAT_MAX_PWR_LVL] == PSTATE_ID_SOC_POWERDN) { /* * Lock scratch registers which hold the CPU vectors. */ tegra_pmc_lock_cpu_vectors(); /* * SMMU configuration. */ tegra_memctrl_setup(); /* * Security configuration to allow DRAM/device access. */ plat_params = bl31_get_plat_params(); tegra_memctrl_tzdram_setup(tegra_bl31_phys_base, plat_params->tzdram_size); } /* * Reset hardware settings. */ tegra_soc_pwr_domain_on_finish(target_state); }