static void tegra_uart_rx_dma_complete(void *args) { struct tegra_uart_port *tup = args; struct uart_port *u = &tup->uport; unsigned long flags; struct dma_tx_state state; enum dma_status status; spin_lock_irqsave(&u->lock, flags); status = dmaengine_tx_status(tup->rx_dma_chan, tup->rx_cookie, &state); if (status == DMA_IN_PROGRESS) { dev_dbg(tup->uport.dev, "RX DMA is in progress\n"); goto done; } /* Deactivate flow control to stop sender */ if (tup->rts_active) set_rts(tup, false); tegra_uart_rx_buffer_push(tup, 0); tegra_uart_start_rx_dma(tup); /* Activate flow control to start transfer */ if (tup->rts_active) set_rts(tup, true); done: spin_unlock_irqrestore(&u->lock, flags); }
static void tegra_uart_handle_rx_dma(struct tegra_uart_port *tup, unsigned long *flags) { struct dma_tx_state state; struct tty_struct *tty = tty_port_tty_get(&tup->uport.state->port); struct tty_port *port = &tup->uport.state->port; struct uart_port *u = &tup->uport; int count; /* Deactivate flow control to stop sender */ if (tup->rts_active) set_rts(tup, false); dmaengine_terminate_all(tup->rx_dma_chan); dmaengine_tx_status(tup->rx_dma_chan, tup->rx_cookie, &state); async_tx_ack(tup->rx_dma_desc); count = tup->rx_bytes_requested - state.residue; /* If we are here, DMA is stopped */ if (count) tegra_uart_copy_rx_to_tty(tup, port, count); tegra_uart_handle_rx_pio(tup, port); if (tty) { spin_unlock_irqrestore(&u->lock, *flags); tty_flip_buffer_push(port); spin_lock_irqsave(&u->lock, *flags); tty_kref_put(tty); } tegra_uart_start_rx_dma(tup); if (tup->rts_active) set_rts(tup, true); }
static void tegra_uart_rx_dma_complete(void *args) { struct tegra_uart_port *tup = args; struct uart_port *u = &tup->uport; int count = tup->rx_bytes_requested; struct tty_struct *tty = tty_port_tty_get(&tup->uport.state->port); struct tty_port *port = &u->state->port; unsigned long flags; async_tx_ack(tup->rx_dma_desc); spin_lock_irqsave(&u->lock, flags); /* Deactivate flow control to stop sender */ if (tup->rts_active) set_rts(tup, false); /* If we are here, DMA is stopped */ if (count) tegra_uart_copy_rx_to_tty(tup, port, count); tegra_uart_handle_rx_pio(tup, port); if (tty) { spin_unlock_irqrestore(&u->lock, flags); tty_flip_buffer_push(port); spin_lock_irqsave(&u->lock, flags); tty_kref_put(tty); } tegra_uart_start_rx_dma(tup); /* Activate flow control to start transfer */ if (tup->rts_active) set_rts(tup, true); spin_unlock_irqrestore(&u->lock, flags); }
static void tegra_uart_rx_dma_complete(void *args) { struct tegra_uart_port *tup = args; struct uart_port *u = &tup->uport; int count = tup->rx_bytes_requested; struct tty_struct *tty = tty_port_tty_get(&tup->uport.state->port); struct tty_port *port = &u->state->port; unsigned long flags; int rx_level = 0; struct dma_tx_state state; enum dma_status status; spin_lock_irqsave(&u->lock, flags); async_tx_ack(tup->rx_dma_desc); status = dmaengine_tx_status(tup->rx_dma_chan, tup->rx_cookie, &state); if (status == DMA_IN_PROGRESS) { dev_info(tup->uport.dev, "RX DMA is in progress\n"); goto done; } /* Deactivate flow control to stop sender */ if (tup->rts_active) set_rts(tup, false); /* If we are here, DMA is stopped */ if (count) tegra_uart_copy_rx_to_tty(tup, port, count); tegra_uart_handle_rx_pio(tup, port); if (tup->enable_rx_buffer_throttle) { rx_level = tty_buffer_get_level(port); if (rx_level > 70) mod_timer(&tup->timer, jiffies + tup->timer_timeout_jiffies); } if (tty) { tty_flip_buffer_push(port); tty_kref_put(tty); } tegra_uart_start_rx_dma(tup); /* Activate flow control to start transfer */ if (tup->enable_rx_buffer_throttle) { if ((rx_level <= 70) && tup->rts_active) set_rts(tup, true); } else if (tup->rts_active) set_rts(tup, true); done: spin_unlock_irqrestore(&u->lock, flags); }
static void tegra_uart_handle_rx_dma(struct tegra_uart_port *tup) { struct dma_tx_state state; /* Deactivate flow control to stop sender */ if (tup->rts_active) set_rts(tup, false); dmaengine_terminate_all(tup->rx_dma_chan); dmaengine_tx_status(tup->rx_dma_chan, tup->rx_cookie, &state); tegra_uart_rx_buffer_push(tup, state.residue); tegra_uart_start_rx_dma(tup); if (tup->rts_active) set_rts(tup, true); }
static void tegra_uart_handle_rx_dma(struct tegra_uart_port *tup) { struct dma_tx_state state; struct tty_struct *tty = tty_port_tty_get(&tup->uport.state->port); struct tty_port *port = &tup->uport.state->port; int count; int rx_level = 0; /* Deactivate flow control to stop sender */ if (tup->rts_active) set_rts(tup, false); dmaengine_terminate_all(tup->rx_dma_chan); dmaengine_tx_status(tup->rx_dma_chan, tup->rx_cookie, &state); async_tx_ack(tup->rx_dma_desc); count = tup->rx_bytes_requested - state.residue; /* If we are here, DMA is stopped */ if (count) tegra_uart_copy_rx_to_tty(tup, port, count); tegra_uart_handle_rx_pio(tup, port); if (tup->enable_rx_buffer_throttle) { rx_level = tty_buffer_get_level(port); if (rx_level > 70) mod_timer(&tup->timer, jiffies + tup->timer_timeout_jiffies); } if (tty) { tty_flip_buffer_push(port); tty_kref_put(tty); } tegra_uart_start_rx_dma(tup); if (tup->enable_rx_buffer_throttle) { if ((rx_level <= 70) && tup->rts_active) set_rts(tup, true); } else if (tup->rts_active) set_rts(tup, true); }
static int tegra_uart_hw_init(struct tegra_uart_port *tup) { int ret; tup->fcr_shadow = 0; tup->mcr_shadow = 0; tup->lcr_shadow = 0; tup->ier_shadow = 0; tup->current_baud = 0; clk_prepare_enable(tup->uart_clk); /* Reset the UART controller to clear all previous status.*/ reset_control_assert(tup->rst); udelay(10); reset_control_deassert(tup->rst); tup->rx_in_progress = 0; tup->tx_in_progress = 0; /* * Set the trigger level * * For PIO mode: * * For receive, this will interrupt the CPU after that many number of * bytes are received, for the remaining bytes the receive timeout * interrupt is received. Rx high watermark is set to 4. * * For transmit, if the trasnmit interrupt is enabled, this will * interrupt the CPU when the number of entries in the FIFO reaches the * low watermark. Tx low watermark is set to 16 bytes. * * For DMA mode: * * Set the Tx trigger to 16. This should match the DMA burst size that * programmed in the DMA registers. */ tup->fcr_shadow = UART_FCR_ENABLE_FIFO; tup->fcr_shadow |= UART_FCR_R_TRIG_01; tup->fcr_shadow |= TEGRA_UART_TX_TRIG_16B; tegra_uart_write(tup, tup->fcr_shadow, UART_FCR); /* Dummy read to ensure the write is posted */ tegra_uart_read(tup, UART_SCR); /* * For all tegra devices (up to t210), there is a hardware issue that * requires software to wait for 3 UART clock periods after enabling * the TX fifo, otherwise data could be lost. */ tegra_uart_wait_cycle_time(tup, 3); /* * Initialize the UART with default configuration * (115200, N, 8, 1) so that the receive DMA buffer may be * enqueued */ tup->lcr_shadow = TEGRA_UART_DEFAULT_LSR; tegra_set_baudrate(tup, TEGRA_UART_DEFAULT_BAUD); tup->fcr_shadow |= UART_FCR_DMA_SELECT; tegra_uart_write(tup, tup->fcr_shadow, UART_FCR); ret = tegra_uart_start_rx_dma(tup); if (ret < 0) { dev_err(tup->uport.dev, "Not able to start Rx DMA\n"); return ret; } tup->rx_in_progress = 1; /* * Enable IE_RXS for the receive status interrupts like line errros. * Enable IE_RX_TIMEOUT to get the bytes which cannot be DMA'd. * * If using DMA mode, enable EORD instead of receive interrupt which * will interrupt after the UART is done with the receive instead of * the interrupt when the FIFO "threshold" is reached. * * EORD is different interrupt than RX_TIMEOUT - RX_TIMEOUT occurs when * the DATA is sitting in the FIFO and couldn't be transferred to the * DMA as the DMA size alignment(4 bytes) is not met. EORD will be * triggered when there is a pause of the incomming data stream for 4 * characters long. * * For pauses in the data which is not aligned to 4 bytes, we get * both the EORD as well as RX_TIMEOUT - SW sees RX_TIMEOUT first * then the EORD. */ tup->ier_shadow = UART_IER_RLSI | UART_IER_RTOIE | TEGRA_UART_IER_EORD; tegra_uart_write(tup, tup->ier_shadow, UART_IER); return 0; }