void ti85_state::update_ti83p_memory () { address_space &space = m_maincpu->space(AS_PROGRAM); if (m_ti8x_memory_page_1 & 0x40) { ti8x_update_bank(space, (m_ti83p_port4 & 1) ? 2 : 1, m_ti8x_ram, m_ti8x_memory_page_1 & 0x01, true); } else { ti8x_update_bank(space, (m_ti83p_port4 & 1) ? 2 : 1, m_bios, m_ti8x_memory_page_1 & 0x1f, false); } if (m_ti8x_memory_page_2 & 0x40) { ti8x_update_bank(space, (m_ti83p_port4 & 1) ? 3 : 2, m_ti8x_ram, m_ti8x_memory_page_2 & 0x01, true); } else { ti8x_update_bank(space, (m_ti83p_port4 & 1) ? 3 : 2, m_bios, m_ti8x_memory_page_2 & 0x1f, false); } }
void ti85_state::update_ti86_memory () { address_space &space = m_maincpu->space(AS_PROGRAM); if (m_ti8x_memory_page_1 & 0x40) { ti8x_update_bank(space, 1, m_ti8x_ram, m_ti8x_memory_page_1 & 0x07, true); } else { ti8x_update_bank(space, 1, m_bios, m_ti8x_memory_page_1 & 0x0f, false); } if (m_ti8x_memory_page_2 & 0x40) { ti8x_update_bank(space, 2, m_ti8x_ram, m_ti8x_memory_page_2 & 0x07, true); } else { ti8x_update_bank(space, 2, m_bios, m_ti8x_memory_page_2 & 0x0f, false); } }
static void update_ti83p_memory (running_machine &machine) { ti85_state *state = machine.driver_data<ti85_state>(); address_space &space = state->m_maincpu->space(AS_PROGRAM); if (state->m_ti8x_memory_page_1 & 0x40) { ti8x_update_bank(space, (state->m_ti83p_port4 & 1) ? 2 : 1, state->m_ti8x_ram, state->m_ti8x_memory_page_1 & 0x01, true); } else { ti8x_update_bank(space, (state->m_ti83p_port4 & 1) ? 2 : 1, state->m_bios, state->m_ti8x_memory_page_1 & 0x1f, false); } if (state->m_ti8x_memory_page_2 & 0x40) { ti8x_update_bank(space, (state->m_ti83p_port4 & 1) ? 3 : 2, state->m_ti8x_ram, state->m_ti8x_memory_page_2 & 0x01, true); } else { ti8x_update_bank(space, (state->m_ti83p_port4 & 1) ? 3 : 2, state->m_bios, state->m_ti8x_memory_page_2 & 0x1f, false); } }