/** * ti_gpio_pin_toggle - Toggles a given GPIO pin * @dev: gpio device handle * @pin: the number of the pin * * * LOCKING: * Internally locks the context * * RETURNS: * Returns 0 on success otherwise a error code */ static int ti_gpio_pin_toggle(device_t dev, uint32_t pin) { struct ti_gpio_softc *sc = device_get_softc(dev); uint32_t bank = (pin / PINS_PER_BANK); uint32_t mask = (1UL << (pin % PINS_PER_BANK)); uint32_t val; TI_GPIO_LOCK(sc); /* Sanity check the pin number is valid */ if ((bank >= MAX_GPIO_BANKS) || (sc->sc_mem_res[bank] == NULL)) { TI_GPIO_UNLOCK(sc); return (EINVAL); } /* Toggle the pin */ val = ti_gpio_read_4(sc, bank, TI_GPIO_DATAOUT); if (val & mask) ti_gpio_write_4(sc, bank, TI_GPIO_CLEARDATAOUT, mask); else ti_gpio_write_4(sc, bank, TI_GPIO_SETDATAOUT, mask); TI_GPIO_UNLOCK(sc); return (0); }
/** * ti_gpio_detach - detach function for the driver * @dev: scm device handle * * Allocates and sets up the driver context, this simply entails creating a * bus mappings for the SCM register set. * * LOCKING: * None * * RETURNS: * Always returns 0 */ static int ti_gpio_detach(device_t dev) { struct ti_gpio_softc *sc = device_get_softc(dev); unsigned int i; KASSERT(mtx_initialized(&sc->sc_mtx), ("gpio mutex not initialized")); /* Disable all interrupts */ for (i = 0; i < MAX_GPIO_BANKS; i++) { if (sc->sc_mem_res[i] != NULL) { ti_gpio_write_4(sc, i, TI_GPIO_CLEARIRQENABLE1, 0xffffffff); ti_gpio_write_4(sc, i, TI_GPIO_CLEARIRQENABLE2, 0xffffffff); } } bus_generic_detach(dev); /* Release the memory and IRQ resources */ for (i = 0; i < MAX_GPIO_BANKS; i++) { if (sc->sc_mem_res[i] != NULL) bus_release_resource(dev, SYS_RES_MEMORY, i, sc->sc_mem_res[i]); if (sc->sc_irq_res[i] != NULL) bus_release_resource(dev, SYS_RES_IRQ, i, sc->sc_irq_res[i]); } TI_GPIO_LOCK_DESTROY(sc); return (0); }
static inline void ti_gpio_intr_clr(struct ti_gpio_softc *sc, uint32_t mask) { /* We clear both set of registers. */ ti_gpio_write_4(sc, TI_GPIO_IRQSTATUS_CLR_0, mask); ti_gpio_write_4(sc, TI_GPIO_IRQSTATUS_CLR_1, mask); }
static int ti_gpio_bank_init(device_t dev) { int pin; struct ti_gpio_softc *sc; uint32_t flags, reg_oe, reg_set, rev; clk_ident_t clk; sc = device_get_softc(dev); /* Enable the interface and functional clocks for the module. */ clk = ti_hwmods_get_clock(dev); if (clk == INVALID_CLK_IDENT) { device_printf(dev, "failed to get device id based on ti,hwmods\n"); return (EINVAL); } sc->sc_bank = clk - GPIO1_CLK + ti_first_gpio_bank(); ti_prcm_clk_enable(clk); /* * Read the revision number of the module. TI don't publish the * actual revision numbers, so instead the values have been * determined by experimentation. */ rev = ti_gpio_read_4(sc, TI_GPIO_REVISION); /* Check the revision. */ if (rev != ti_gpio_rev()) { device_printf(dev, "Warning: could not determine the revision " "of GPIO module (revision:0x%08x)\n", rev); return (EINVAL); } /* Disable interrupts for all pins. */ ti_gpio_intr_clr(sc, 0xffffffff); /* Init OE register based on pads configuration. */ reg_oe = 0xffffffff; reg_set = 0; for (pin = 0; pin < PINS_PER_BANK; pin++) { TI_GPIO_GET_FLAGS(dev, pin, &flags); if (flags & GPIO_PIN_OUTPUT) { reg_oe &= ~(1UL << pin); if (flags & GPIO_PIN_PULLUP) reg_set |= (1UL << pin); } } ti_gpio_write_4(sc, TI_GPIO_OE, reg_oe); if (reg_set) ti_gpio_write_4(sc, TI_GPIO_SETDATAOUT, reg_set); return (0); }
static inline void ti_gpio_intr_ack(struct ti_gpio_softc *sc, uint32_t mask) { /* * Acknowledge the interrupt on both registers even if we use only * the first one. */ ti_gpio_write_4(sc, TI_GPIO_IRQSTATUS_0, mask); ti_gpio_write_4(sc, TI_GPIO_IRQSTATUS_1, mask); }
static inline void ti_gpio_intr_clr(struct ti_gpio_softc *sc, unsigned int bank, uint32_t mask) { /* We clear both set of registers. */ #if defined(SOC_OMAP4) || defined(SOC_TI_AM335X) ti_gpio_write_4(sc, bank, TI_GPIO_IRQSTATUS_CLR_0, mask); ti_gpio_write_4(sc, bank, TI_GPIO_IRQSTATUS_CLR_1, mask); #else ti_gpio_write_4(sc, bank, TI_GPIO_CLEARIRQENABLE1, mask); ti_gpio_write_4(sc, bank, TI_GPIO_CLEARIRQENABLE2, mask); #endif }
/** * ti_gpio_pin_setflags - Sets the flags for a given pin * @dev: gpio device handle * @pin: the number of the pin * @flags: the flags to set * * The flags of the pin correspond to things like input/output mode, pull-ups, * pull-downs, etc. This driver doesn't support all flags, only the following: * - GPIO_PIN_INPUT * - GPIO_PIN_OUTPUT * - GPIO_PIN_PULLUP * - GPIO_PIN_PULLDOWN * * LOCKING: * Internally locks the context * * RETURNS: * Returns 0 on success otherwise an error code */ static int ti_gpio_pin_setflags(device_t dev, uint32_t pin, uint32_t flags) { struct ti_gpio_softc *sc = device_get_softc(dev); uint32_t bank = (pin / PINS_PER_BANK); uint32_t mask = (1UL << (pin % PINS_PER_BANK)); uint32_t reg_val; TI_GPIO_LOCK(sc); /* Sanity check the pin number is valid */ if ((bank >= MAX_GPIO_BANKS) || (sc->sc_mem_res[bank] == NULL)) { TI_GPIO_UNLOCK(sc); return (EINVAL); } /* Set the GPIO mode and state */ if (ti_scm_padconf_set_gpioflags(pin, flags) != 0) { TI_GPIO_UNLOCK(sc); return (EINVAL); } /* If configuring as an output set the "output enable" bit */ reg_val = ti_gpio_read_4(sc, bank, TI_GPIO_OE); if (flags & GPIO_PIN_INPUT) reg_val |= mask; else reg_val &= ~mask; ti_gpio_write_4(sc, bank, TI_GPIO_OE, reg_val); TI_GPIO_UNLOCK(sc); return (0); }
/** * ti_gpio_pin_setflags - Sets the flags for a given pin * @dev: gpio device handle * @pin: the number of the pin * @flags: the flags to set * * The flags of the pin correspond to things like input/output mode, pull-ups, * pull-downs, etc. This driver doesn't support all flags, only the following: * - GPIO_PIN_INPUT * - GPIO_PIN_OUTPUT * - GPIO_PIN_PULLUP * - GPIO_PIN_PULLDOWN * * LOCKING: * Internally locks the context * * RETURNS: * Returns 0 on success otherwise an error code */ static int ti_gpio_pin_setflags(device_t dev, uint32_t pin, uint32_t flags) { struct ti_gpio_softc *sc; uint32_t oe; sc = device_get_softc(dev); if (ti_gpio_valid_pin(sc, pin) != 0) return (EINVAL); /* Set the GPIO mode and state */ TI_GPIO_LOCK(sc); if (TI_GPIO_SET_FLAGS(dev, pin, flags) != 0) { TI_GPIO_UNLOCK(sc); return (EINVAL); } /* If configuring as an output set the "output enable" bit */ oe = ti_gpio_read_4(sc, TI_GPIO_OE); if (flags & GPIO_PIN_INPUT) oe |= TI_GPIO_MASK(pin); else oe &= ~TI_GPIO_MASK(pin); ti_gpio_write_4(sc, TI_GPIO_OE, oe); TI_GPIO_UNLOCK(sc); return (0); }
static inline void ti_gpio_rwreg_modify(struct ti_gpio_softc *sc, uint32_t reg, uint32_t mask, bool set_bits) { uint32_t value; value = ti_gpio_read_4(sc, reg); ti_gpio_write_4(sc, reg, set_bits ? value | mask : value & ~mask); }
static inline void ti_gpio_intr_set(struct ti_gpio_softc *sc, uint32_t mask) { /* * On OMAP4 we unmask only the MPU interrupt and on AM335x we * also activate only the first interrupt. */ ti_gpio_write_4(sc, TI_GPIO_IRQSTATUS_SET_0, mask); }
static int ti_gpio_config_intr(device_t dev, int irq, enum intr_trigger trig, enum intr_polarity pol) { struct ti_gpio_softc *sc; uint32_t oldreg, reg, val; sc = device_get_softc(dev); if (ti_gpio_valid_pin(sc, irq) != 0) return (EINVAL); /* There is no standard trigger or polarity. */ if (trig == INTR_TRIGGER_CONFORM || pol == INTR_POLARITY_CONFORM) return (EINVAL); TI_GPIO_LOCK(sc); /* * TRM recommends add the new event before remove the old one to * avoid losing interrupts. */ oldreg = ti_gpio_intr_reg(sc, irq); sc->sc_irq_trigger[irq] = trig; sc->sc_irq_polarity[irq] = pol; reg = ti_gpio_intr_reg(sc, irq); if (reg != 0) { /* Apply the new settings. */ val = ti_gpio_read_4(sc, reg); val |= TI_GPIO_MASK(irq); ti_gpio_write_4(sc, reg, val); } if (reg != oldreg && oldreg != 0) { /* Remove the old settings. */ val = ti_gpio_read_4(sc, oldreg); val &= ~TI_GPIO_MASK(irq); ti_gpio_write_4(sc, oldreg, val); } TI_GPIO_UNLOCK(sc); return (0); }
static void ti_gpio_unmask_irq_internal(struct ti_gpio_softc *sc, int irq) { uint32_t reg, val; if (ti_gpio_valid_pin(sc, irq) != 0) return; TI_GPIO_LOCK(sc); reg = ti_gpio_intr_reg(sc, irq); if (reg != 0) { val = ti_gpio_read_4(sc, reg); val |= TI_GPIO_MASK(irq); ti_gpio_write_4(sc, reg, val); ti_gpio_intr_set(sc, TI_GPIO_MASK(irq)); } TI_GPIO_UNLOCK(sc); }
/** * ti_gpio_pin_setflags - Sets the flags for a given pin * @dev: gpio device handle * @pin: the number of the pin * @flags: the flags to set * * The flags of the pin correspond to things like input/output mode, pull-ups, * pull-downs, etc. This driver doesn't support all flags, only the following: * - GPIO_PIN_INPUT * - GPIO_PIN_OUTPUT * - GPIO_PIN_PULLUP * - GPIO_PIN_PULLDOWN * * LOCKING: * Internally locks the context * * RETURNS: * Returns 0 on success otherwise an error code */ static int ti_gpio_pin_setflags(device_t dev, uint32_t pin, uint32_t flags) { struct ti_gpio_softc *sc = device_get_softc(dev); uint32_t bank = (pin / PINS_PER_BANK); uint32_t mask = (1UL << (pin % PINS_PER_BANK)); uint32_t reg_val; /* Sanity check the flags supplied are valid, i.e. not input and output */ if ((flags & (GPIO_PIN_INPUT|GPIO_PIN_OUTPUT)) == 0x0000) return (EINVAL); if ((flags & (GPIO_PIN_INPUT|GPIO_PIN_OUTPUT)) == (GPIO_PIN_INPUT|GPIO_PIN_OUTPUT)) return (EINVAL); if ((flags & (GPIO_PIN_PULLUP|GPIO_PIN_PULLDOWN)) == (GPIO_PIN_PULLUP|GPIO_PIN_PULLDOWN)) return (EINVAL); TI_GPIO_LOCK(sc); /* Sanity check the pin number is valid */ if ((bank >= ti_max_gpio_banks()) || (sc->sc_mem_res[bank] == NULL)) { TI_GPIO_UNLOCK(sc); return (EINVAL); } /* Set the GPIO mode and state */ if (TI_GPIO_SET_FLAGS(dev, pin, flags) != 0) { TI_GPIO_UNLOCK(sc); return (EINVAL); } /* If configuring as an output set the "output enable" bit */ reg_val = ti_gpio_read_4(sc, bank, TI_GPIO_OE); if (flags & GPIO_PIN_INPUT) reg_val |= mask; else reg_val &= ~mask; ti_gpio_write_4(sc, bank, TI_GPIO_OE, reg_val); TI_GPIO_UNLOCK(sc); return (0); }
static int ti_gpio_bank_init(device_t dev, int bank) { int pin; struct ti_gpio_softc *sc; uint32_t flags, reg_oe; sc = device_get_softc(dev); /* Enable the interface and functional clocks for the module. */ ti_prcm_clk_enable(GPIO0_CLK + FIRST_GPIO_BANK + bank); /* * Read the revision number of the module. TI don't publish the * actual revision numbers, so instead the values have been * determined by experimentation. */ sc->sc_revision[bank] = ti_gpio_read_4(sc, bank, TI_GPIO_REVISION); /* Check the revision. */ if (sc->sc_revision[bank] != TI_GPIO_REV) { device_printf(dev, "Warning: could not determine the revision " "of %u GPIO module (revision:0x%08x)\n", bank, sc->sc_revision[bank]); return (EINVAL); } /* Disable interrupts for all pins. */ ti_gpio_intr_clr(sc, bank, 0xffffffff); /* Init OE register based on pads configuration. */ reg_oe = 0xffffffff; for (pin = 0; pin < PINS_PER_BANK; pin++) { ti_scm_padconf_get_gpioflags(PINS_PER_BANK * bank + pin, &flags); if (flags & GPIO_PIN_OUTPUT) reg_oe &= ~(1UL << pin); } ti_gpio_write_4(sc, bank, TI_GPIO_OE, reg_oe); return (0); }
/** * ti_gpio_pin_set - Sets the current level on a GPIO pin * @dev: gpio device handle * @pin: the number of the pin * @value: non-zero value will drive the pin high, otherwise the pin is * driven low. * * * LOCKING: * Internally locks the context * * RETURNS: * Returns 0 on success otherwise a error code */ static int ti_gpio_pin_set(device_t dev, uint32_t pin, unsigned int value) { struct ti_gpio_softc *sc; uint32_t reg; sc = device_get_softc(dev); if (ti_gpio_valid_pin(sc, pin) != 0) return (EINVAL); TI_GPIO_LOCK(sc); if (value == GPIO_PIN_LOW) reg = TI_GPIO_CLEARDATAOUT; else reg = TI_GPIO_SETDATAOUT; ti_gpio_write_4(sc, reg, TI_GPIO_MASK(pin)); TI_GPIO_UNLOCK(sc); return (0); }
/** * ti_gpio_pin_set - Sets the current level on a GPIO pin * @dev: gpio device handle * @pin: the number of the pin * @value: non-zero value will drive the pin high, otherwise the pin is * driven low. * * * LOCKING: * Internally locks the context * * RETURNS: * Returns 0 on success otherwise a error code */ static int ti_gpio_pin_set(device_t dev, uint32_t pin, unsigned int value) { struct ti_gpio_softc *sc = device_get_softc(dev); uint32_t bank = (pin / PINS_PER_BANK); uint32_t mask = (1UL << (pin % PINS_PER_BANK)); TI_GPIO_LOCK(sc); /* Sanity check the pin number is valid */ if ((bank >= MAX_GPIO_BANKS) || (sc->sc_mem_res[bank] == NULL)) { TI_GPIO_UNLOCK(sc); return (EINVAL); } ti_gpio_write_4(sc, bank, (value == GPIO_PIN_LOW) ? TI_GPIO_CLEARDATAOUT : TI_GPIO_SETDATAOUT, mask); TI_GPIO_UNLOCK(sc); return (0); }
/** * ti_gpio_pin_toggle - Toggles a given GPIO pin * @dev: gpio device handle * @pin: the number of the pin * * * LOCKING: * Internally locks the context * * RETURNS: * Returns 0 on success otherwise a error code */ static int ti_gpio_pin_toggle(device_t dev, uint32_t pin) { struct ti_gpio_softc *sc; uint32_t reg, val; sc = device_get_softc(dev); if (ti_gpio_valid_pin(sc, pin) != 0) return (EINVAL); /* Toggle the pin */ TI_GPIO_LOCK(sc); val = ti_gpio_read_4(sc, TI_GPIO_DATAOUT); if (val & TI_GPIO_MASK(pin)) reg = TI_GPIO_CLEARDATAOUT; else reg = TI_GPIO_SETDATAOUT; ti_gpio_write_4(sc, reg, TI_GPIO_MASK(pin)); TI_GPIO_UNLOCK(sc); return (0); }
/** * ti_gpio_attach - attach function for the driver * @dev: gpio device handle * * Allocates and sets up the driver context for all GPIO banks. This function * expects the memory ranges and IRQs to already be allocated to the driver. * * LOCKING: * None * * RETURNS: * Always returns 0 */ static int ti_gpio_attach(device_t dev) { struct ti_gpio_softc *sc = device_get_softc(dev); unsigned int i; int err = 0; int pin; uint32_t flags; uint32_t reg_oe; sc->sc_dev = dev; TI_GPIO_LOCK_INIT(sc); /* There are up to 6 different GPIO register sets located in different * memory areas on the chip. The memory range should have been set for * the driver when it was added as a child. */ err = bus_alloc_resources(dev, ti_gpio_mem_spec, sc->sc_mem_res); if (err) { device_printf(dev, "Error: could not allocate mem resources\n"); return (ENXIO); } /* Request the IRQ resources */ err = bus_alloc_resources(dev, ti_gpio_irq_spec, sc->sc_irq_res); if (err) { device_printf(dev, "Error: could not allocate irq resources\n"); return (ENXIO); } /* Setup the IRQ resources */ for (i = 0; i < MAX_GPIO_BANKS; i++) { if (sc->sc_irq_res[i] == NULL) break; /* Register an interrupt handler for each of the IRQ resources */ if ((bus_setup_intr(dev, sc->sc_irq_res[i], INTR_TYPE_MISC | INTR_MPSAFE, NULL, ti_gpio_intr, sc, &(sc->sc_irq_hdl[i])))) { device_printf(dev, "WARNING: unable to register interrupt handler\n"); return (ENXIO); } } /* We need to go through each block and ensure the clocks are running and * the module is enabled. It might be better to do this only when the * pins are configured which would result in less power used if the GPIO * pins weren't used ... */ for (i = 0; i < MAX_GPIO_BANKS; i++) { if (sc->sc_mem_res[i] != NULL) { /* Enable the interface and functional clocks for the module */ ti_prcm_clk_enable(GPIO0_CLK + FIRST_GPIO_BANK + i); /* Read the revision number of the module. TI don't publish the * actual revision numbers, so instead the values have been * determined by experimentation. */ sc->sc_revision[i] = ti_gpio_read_4(sc, i, TI_GPIO_REVISION); /* Check the revision */ if (sc->sc_revision[i] != TI_GPIO_REV) { device_printf(dev, "Warning: could not determine the revision" "of %u GPIO module (revision:0x%08x)\n", i, sc->sc_revision[i]); continue; } /* Disable interrupts for all pins */ ti_gpio_write_4(sc, i, TI_GPIO_CLEARIRQENABLE1, 0xffffffff); ti_gpio_write_4(sc, i, TI_GPIO_CLEARIRQENABLE2, 0xffffffff); /* Init OE register based on pads configuration */ reg_oe = 0xffffffff; for (pin = 0; pin < 32; pin++) { ti_scm_padconf_get_gpioflags( PINS_PER_BANK*i + pin, &flags); if (flags & GPIO_PIN_OUTPUT) reg_oe &= ~(1U << pin); } ti_gpio_write_4(sc, i, TI_GPIO_OE, reg_oe); } } /* Finish of the probe call */ device_add_child(dev, "gpioc", device_get_unit(dev)); device_add_child(dev, "gpiobus", device_get_unit(dev)); return (bus_generic_attach(dev)); }