/* * Notify all modules that we're back on and rely on them to restore clocks * and power domains as required. */ static void wake_up(void) { lpm_registered_module_t *module; /* Remember IRQ energest for next pass */ ENERGEST_IRQ_SAVE(irq_energest); ENERGEST_ON(ENERGEST_TYPE_CPU); ENERGEST_OFF(ENERGEST_TYPE_LPM); /* Sync so that we get the latest values before adjusting recharge settings */ ti_lib_sys_ctrl_aon_sync(); /* Adjust recharge settings */ ti_lib_sys_ctrl_adjust_recharge_after_power_down(); /* * Release the request to the uLDO * This is likely not required, since the switch to GLDO/DCDC is automatic * when coming back from deep sleep */ ti_lib_prcm_mcu_uldo_configure(false); /* Turn on cache again */ ti_lib_vims_mode_set(VIMS_BASE, VIMS_MODE_ENABLED); ti_lib_prcm_cache_retention_enable(); ti_lib_aon_ioc_freeze_disable(); ti_lib_sys_ctrl_aon_sync(); /* Check operating conditions, optimally choose DCDC versus GLDO */ ti_lib_sys_ctrl_dcdc_voltage_conditional_control(); /* * We may or may not have been woken up by an AON RTC tick. If not, we need * to adjust our software tick counter */ clock_update(); watchdog_periodic(); /* Notify all registered modules that we've just woken up */ for(module = list_head(modules_list); module != NULL; module = module->next) { if(module->wakeup) { module->wakeup(); } } }
/** * \brief Main function for CC26xx-based platforms * * The same main() is used for all supported boards */ int main(void) { /* Enable flash cache and prefetch. */ ti_lib_vims_mode_set(VIMS_BASE, VIMS_MODE_ENABLED); ti_lib_vims_configure(VIMS_BASE, true, true); ti_lib_int_master_disable(); /* Set the LF XOSC as the LF system clock source */ oscillators_select_lf_xosc(); lpm_init(); board_init(); gpio_interrupt_init(); leds_init(); /* * Disable I/O pad sleep mode and open I/O latches in the AON IOC interface * This is only relevant when returning from shutdown (which is what froze * latches in the first place. Before doing these things though, we should * allow software to first regain control of pins */ ti_lib_pwr_ctrl_io_freeze_disable(); fade(LEDS_RED); ti_lib_int_master_enable(); soc_rtc_init(); clock_init(); rtimer_init(); watchdog_init(); process_init(); random_init(0x1234); /* Character I/O Initialisation */ #if CC26XX_UART_CONF_ENABLE cc26xx_uart_init(); #endif serial_line_init(); printf("Starting " CONTIKI_VERSION_STRING "\n\r"); printf("With DriverLib v%u.%u\n\r", DRIVERLIB_RELEASE_GROUP, DRIVERLIB_RELEASE_BUILD); printf(BOARD_STRING "\n\r"); process_start(&etimer_process, NULL); ctimer_init(); energest_init(); ENERGEST_ON(ENERGEST_TYPE_CPU); fade(LEDS_YELLOW); printf(" Net: "); printf("%s\n\r", NETSTACK_NETWORK.name); printf(" MAC: "); printf("%s\n\r", NETSTACK_MAC.name); printf(" RDC: "); printf("%s", NETSTACK_RDC.name); if(NETSTACK_RDC.channel_check_interval() != 0) { printf(", Channel Check Interval: %u ticks", NETSTACK_RDC.channel_check_interval()); } printf("\n\r"); netstack_init(); set_rf_params(); #if NETSTACK_CONF_WITH_IPV6 memcpy(&uip_lladdr.addr, &linkaddr_node_addr, sizeof(uip_lladdr.addr)); queuebuf_init(); process_start(&tcpip_process, NULL); #endif /* NETSTACK_CONF_WITH_IPV6 */ fade(LEDS_GREEN); process_start(&sensors_process, NULL); autostart_start(autostart_processes); watchdog_start(); fade(LEDS_ORANGE); while(1) { uint8_t r; do { r = process_run(); watchdog_periodic(); } while(r > 0); /* Drop to some low power mode */ lpm_drop(); } }
/*---------------------------------------------------------------------------*/ void lpm_shutdown(uint32_t wakeup_pin, uint32_t io_pull, uint32_t wake_on) { lpm_registered_module_t *module; int i; uint32_t io_cfg = (IOC_STD_INPUT & ~IOC_IOPULL_M) | io_pull | wake_on; /* This procedure may not be interrupted */ ti_lib_int_master_disable(); /* Disable the RTC */ ti_lib_aon_rtc_disable(); ti_lib_aon_rtc_event_clear(AON_RTC_CH0); ti_lib_aon_rtc_event_clear(AON_RTC_CH1); ti_lib_aon_rtc_event_clear(AON_RTC_CH2); /* Reset AON even fabric to default wakeup sources */ for(i = AON_EVENT_MCU_WU0; i <= AON_EVENT_MCU_WU3; i++) { ti_lib_aon_event_mcu_wake_up_set(i, AON_EVENT_NONE); } for(i = AON_EVENT_AUX_WU0; i <= AON_EVENT_AUX_WU2; i++) { ti_lib_aon_event_aux_wake_up_set(i, AON_EVENT_NONE); } ti_lib_sys_ctrl_aon_sync(); watchdog_periodic(); /* Notify all modules that we're shutting down */ for(module = list_head(modules_list); module != NULL; module = module->next) { if(module->shutdown) { module->shutdown(LPM_MODE_SHUTDOWN); } } /* Configure the wakeup trigger */ if(wakeup_pin != IOID_UNUSED) { ti_lib_gpio_dir_mode_set((1 << wakeup_pin), GPIO_DIR_MODE_IN); ti_lib_ioc_port_configure_set(wakeup_pin, IOC_PORT_GPIO, io_cfg); } /* Freeze I/O latches in AON */ ti_lib_aon_ioc_freeze_enable(); /* Turn off RFCORE, SERIAL and PERIPH PDs. This will happen immediately */ ti_lib_prcm_power_domain_off(PRCM_DOMAIN_RFCORE | PRCM_DOMAIN_SERIAL | PRCM_DOMAIN_PERIPH); oscillators_switch_to_hf_rc(); oscillators_select_lf_rcosc(); /* Configure clock sources for MCU and AUX: No clock */ ti_lib_aon_wuc_mcu_power_down_config(AONWUC_NO_CLOCK); ti_lib_aon_wuc_aux_power_down_config(AONWUC_NO_CLOCK); /* Disable SRAM and AUX retentions */ ti_lib_aon_wuc_mcu_sram_config(0); ti_lib_aon_wuc_aux_sram_config(false); /* * Request CPU, SYSBYS and VIMS PD off. * This will only happen when the CM3 enters deep sleep */ ti_lib_prcm_power_domain_off(PRCM_DOMAIN_CPU | PRCM_DOMAIN_VIMS | PRCM_DOMAIN_SYSBUS); /* Request JTAG domain power off */ ti_lib_aon_wuc_jtag_power_off(); /* Turn off AUX */ ti_lib_aux_wuc_power_ctrl(AUX_WUC_POWER_OFF); ti_lib_aon_wuc_domain_power_down_enable(); while(ti_lib_aon_wuc_power_status_get() & AONWUC_AUX_POWER_ON); /* * Request MCU VD power off. * This will only happen when the CM3 enters deep sleep */ ti_lib_prcm_mcu_power_off(); /* Set MCU wakeup to immediate and disable virtual power off */ ti_lib_aon_wuc_mcu_wake_up_config(MCU_IMM_WAKE_UP); ti_lib_aon_wuc_mcu_power_off_config(MCU_VIRT_PWOFF_DISABLE); /* Latch the IOs in the padring and enable I/O pad sleep mode */ ti_lib_pwr_ctrl_io_freeze_enable(); /* Turn off VIMS cache, CRAM and TRAM - possibly not required */ ti_lib_prcm_cache_retention_disable(); ti_lib_vims_mode_set(VIMS_BASE, VIMS_MODE_OFF); /* Enable shutdown and sync AON */ ti_lib_aon_wuc_shut_down_enable(); ti_lib_sys_ctrl_aon_sync(); /* Deep Sleep */ ti_lib_prcm_deep_sleep(); }
/*---------------------------------------------------------------------------*/ void lpm_drop() { lpm_registered_module_t *module; uint8_t max_pm = LPM_MODE_MAX_SUPPORTED; uint8_t module_pm; clock_time_t next_event; uint32_t domains = LOCKABLE_DOMAINS; if(RTIMER_CLOCK_LT(soc_rtc_get_next_trigger(), RTIMER_NOW() + STANDBY_MIN_DURATION)) { lpm_sleep(); return; } /* Collect max allowed PM permission from interested modules */ for(module = list_head(modules_list); module != NULL; module = module->next) { if(module->request_max_pm) { module_pm = module->request_max_pm(); if(module_pm < max_pm) { max_pm = module_pm; } } } /* Check if any events fired during this process. Last chance to abort */ if(process_nevents()) { return; } /* Drop */ if(max_pm == LPM_MODE_SLEEP) { lpm_sleep(); } else { /* Critical. Don't get interrupted! */ ti_lib_int_master_disable(); /* * Reschedule AON RTC CH1 to fire an event N ticks before the next etimer * event */ next_event = etimer_next_expiration_time(); if(next_event) { next_event = next_event - clock_time(); soc_rtc_schedule_one_shot(AON_RTC_CH1, RTIMER_NOW() + (next_event * (RTIMER_SECOND / CLOCK_SECOND))); } /* * Notify all registered modules that we are dropping to mode X. We do not * need to do this for simple sleep. * * This is a chance for modules to delay us a little bit until an ongoing * operation has finished (e.g. uart TX) or to configure themselves for * deep sleep. * * At this stage, we also collect power domain locks, if any. * The argument to PRCMPowerDomainOff() is a bitwise OR, so every time * we encounter a lock we just clear the respective bits in the 'domains' * variable as required by the lock. In the end the domains variable will * just hold whatever has not been cleared */ for(module = list_head(modules_list); module != NULL; module = module->next) { if(module->shutdown) { module->shutdown(max_pm); } /* Clear the bits specified in the lock */ domains &= ~module->domain_lock; } /* Pat the dog: We don't want it to shout right after we wake up */ watchdog_periodic(); /* Clear unacceptable bits, just in case a lock provided a bad value */ domains &= LOCKABLE_DOMAINS; /* * Freeze the IOs on the boundary between MCU and AON. We only do this if * PERIPH is not needed */ if(domains & PRCM_DOMAIN_PERIPH) { ti_lib_aon_ioc_freeze_enable(); } /* * Among LOCKABLE_DOMAINS, turn off those that are not locked * * If domains is != 0, pass it as-is */ if(domains) { ti_lib_prcm_power_domain_off(domains); } /* * Before entering Deep Sleep, we must switch off the HF XOSC. The HF XOSC * is predominantly controlled by the RF driver. In a build with radio * cycling (e.g. ContikiMAC), the RF driver will request the XOSC before * using the Freq. Synth, and switch back to the RC when it is about to * turn back off. * * If the radio is on, we won't even reach here, and if it's off the HF * clock source should already be the HF RC. * * Nevertheless, request the switch to the HF RC explicitly here. */ oscillators_switch_to_hf_rc(); /* Configure clock sources for MCU and AUX: No clock */ ti_lib_aon_wuc_mcu_power_down_config(AONWUC_NO_CLOCK); ti_lib_aon_wuc_aux_power_down_config(AONWUC_NO_CLOCK); /* Full RAM retention. */ ti_lib_aon_wuc_mcu_sram_config(MCU_RAM0_RETENTION | MCU_RAM1_RETENTION | MCU_RAM2_RETENTION | MCU_RAM3_RETENTION); /* Disable retention of AUX RAM */ ti_lib_aon_wuc_aux_sram_config(false); /* * Always turn off RFCORE, CPU, SYSBUS and VIMS. RFCORE should be off * already */ ti_lib_prcm_power_domain_off(PRCM_DOMAIN_RFCORE | PRCM_DOMAIN_CPU | PRCM_DOMAIN_VIMS | PRCM_DOMAIN_SYSBUS); /* Request JTAG domain power off */ ti_lib_aon_wuc_jtag_power_off(); /* Turn off AUX */ ti_lib_aux_wuc_power_ctrl(AUX_WUC_POWER_OFF); ti_lib_aon_wuc_domain_power_down_enable(); while(ti_lib_aon_wuc_power_status_get() & AONWUC_AUX_POWER_ON); /* Configure the recharge controller */ ti_lib_sys_ctrl_set_recharge_before_power_down(XOSC_IN_HIGH_POWER_MODE); /* * If both PERIPH and SERIAL PDs are off, request the uLDO as the power * source while in deep sleep. */ if(domains == LOCKABLE_DOMAINS) { ti_lib_pwr_ctrl_source_set(PWRCTRL_PWRSRC_ULDO); } /* We are only interested in IRQ energest while idle or in LPM */ ENERGEST_IRQ_RESTORE(irq_energest); ENERGEST_SWITCH(ENERGEST_TYPE_CPU, ENERGEST_TYPE_LPM); /* Sync the AON interface to ensure all writes have gone through. */ ti_lib_sys_ctrl_aon_sync(); /* * Explicitly turn off VIMS cache, CRAM and TRAM. Needed because of * retention mismatch between VIMS logic and cache. We wait to do this * until right before deep sleep to be able to use the cache for as long * as possible. */ ti_lib_prcm_cache_retention_disable(); ti_lib_vims_mode_set(VIMS_BASE, VIMS_MODE_OFF); /* Deep Sleep */ ti_lib_prcm_deep_sleep(); /* * When we reach here, some interrupt woke us up. The global interrupt * flag is off, hence we have a chance to run things here. We will wake up * the chip properly, and then we will enable the global interrupt without * unpending events so the handlers can fire */ wake_up(); ti_lib_int_master_enable(); } }
/** * \brief Main function for CC26xx-based platforms * * The same main() is used for both Srf+CC26xxEM as well as for the SensorTag */ int main(void) { /* Set the LF XOSC as the LF system clock source */ select_lf_xosc(); /* * Make sure to open the latches - this will be important when returning * from shutdown */ ti_lib_pwr_ctrl_io_freeze_disable(); /* Use DCDC instead of LDO to save current */ ti_lib_pwr_ctrl_source_set(PWRCTRL_PWRSRC_DCDC); lpm_init(); board_init(); /* Enable flash cache and prefetch. */ ti_lib_vims_mode_set(VIMS_BASE, VIMS_MODE_ENABLED); ti_lib_vims_configure(VIMS_BASE, true, true); gpio_interrupt_init(); /* Clock must always be enabled for the semaphore module */ HWREG(AUX_WUC_BASE + AUX_WUC_O_MODCLKEN1) = AUX_WUC_MODCLKEN1_SMPH; leds_init(); fade(LEDS_RED); cc26xx_rtc_init(); clock_init(); rtimer_init(); watchdog_init(); process_init(); random_init(0x1234); /* Character I/O Initialisation */ #if CC26XX_UART_CONF_ENABLE cc26xx_uart_init(); cc26xx_uart_set_input(serial_line_input_byte); #endif serial_line_init(); printf("Starting " CONTIKI_VERSION_STRING "\n"); printf("With DriverLib v%u.%02u.%02u.%u\n", DRIVERLIB_MAJOR_VER, DRIVERLIB_MINOR_VER, DRIVERLIB_PATCH_VER, DRIVERLIB_BUILD_ID); printf(BOARD_STRING " using CC%u\n", CC26XX_MODEL_CPU_VARIANT); process_start(&etimer_process, NULL); ctimer_init(); energest_init(); ENERGEST_ON(ENERGEST_TYPE_CPU); fade(LEDS_YELLOW); printf(" Net: "); printf("%s\n", NETSTACK_NETWORK.name); printf(" MAC: "); printf("%s\n", NETSTACK_MAC.name); printf(" RDC: "); printf("%s", NETSTACK_RDC.name); if(NETSTACK_RDC.channel_check_interval() != 0) { printf(", Channel Check Interval: %u ticks", NETSTACK_RDC.channel_check_interval()); } printf("\n"); netstack_init(); set_rf_params(); #if NETSTACK_CONF_WITH_IPV6 memcpy(&uip_lladdr.addr, &linkaddr_node_addr, sizeof(uip_lladdr.addr)); queuebuf_init(); process_start(&tcpip_process, NULL); #endif /* NETSTACK_CONF_WITH_IPV6 */ fade(LEDS_GREEN); process_start(&sensors_process, NULL); autostart_start(autostart_processes); watchdog_start(); fade(LEDS_ORANGE); while(1) { uint8_t r; do { r = process_run(); watchdog_periodic(); } while(r > 0); /* Drop to some low power mode */ lpm_drop(); } }