/** * * @brief Initialize and enable the system clock * * This routine is used to program the ARCv2 timer to deliver interrupts at the * rate specified via the 'sys_clock_us_per_tick' global variable. * * @return 0 */ int _sys_clock_driver_init(struct device *device) { ARG_UNUSED(device); /* ensure that the timer will not generate interrupts */ timer0_control_register_set(0); timer0_count_register_set(0); cycles_per_tick = sys_clock_hw_cycles_per_tick; IRQ_CONNECT(IRQ_TIMER0, CONFIG_ARCV2_TIMER_IRQ_PRIORITY, _timer_int_handler, NULL, 0); /* * Set the reload value to achieve the configured tick rate, enable the * counter and interrupt generation. */ tickless_idle_init(); timer0_limit_register_set(cycles_per_tick - 1); timer0_control_register_set(_ARC_V2_TMR_CTRL_NH | _ARC_V2_TMR_CTRL_IE); /* everything has been configured: safe to enable the interrupt */ irq_enable(IRQ_TIMER0); return 0; }
/** * * @brief Initialize and enable the system clock * * This routine is used to program the timer to deliver interrupts at the * rate specified via the 'sys_clock_us_per_tick' global variable. * * @return 0 */ int _sys_clock_driver_init(struct device *device) { ARG_UNUSED(device); /* determine the timer counter value (in timer clock cycles/system tick) */ cycles_per_tick = sys_clock_hw_cycles_per_tick; tickless_idle_init(); #ifndef CONFIG_MVIC divide_configuration_register_set(); #endif initial_count_register_set(cycles_per_tick - 1); periodic_mode_set(); #ifdef CONFIG_DEVICE_POWER_MANAGEMENT loapic_timer_device_power_state = DEVICE_PM_ACTIVE_STATE; #endif IRQ_CONNECT(TIMER_IRQ, TIMER_IRQ_PRIORITY, _timer_int_handler, 0, 0); /* Everything has been configured. It is now safe to enable the * interrupt */ irq_enable(TIMER_IRQ); return 0; }
/** * * @brief Initialize and enable the system clock * * This routine is used to program the timer to deliver interrupts at the * rate specified via the 'sys_clock_us_per_tick' global variable. * * @return 0 */ int _sys_clock_driver_init(struct device *device) { ARG_UNUSED(device); /* determine the timer counter value (in timer clock cycles/system tick) */ cycles_per_tick = sys_clock_hw_cycles_per_tick; tickless_idle_init(); divide_configuration_register_set(); initial_count_register_set(cycles_per_tick - 1); periodic_mode_set(); IRQ_CONNECT(CONFIG_LOAPIC_TIMER_IRQ, CONFIG_LOAPIC_TIMER_IRQ_PRIORITY, _timer_int_handler, 0, 0); /* Everything has been configured. It is now safe to enable the * interrupt */ irq_enable(CONFIG_LOAPIC_TIMER_IRQ); return 0; }