/* * Another ms timer, this one used to generate an overflow interrupt at 1ms * It is used to toggle leds and write tick counts */ static void setup_tim6(void) { timer_reset(TIM6); /* 24Mhz / 10khz -1. */ timer_set_prescaler(TIM6, 2399); /* 24Mhz/10000hz - 1 */ /* 10khz for 10 ticks = 1 khz overflow = 1ms overflow interrupts */ timer_set_period(TIM6, 10); nvic_enable_irq(NVIC_TIM6_IRQ); timer_enable_update_event(TIM6); /* default at reset! */ timer_enable_irq(TIM6, TIM_DIER_UIE); timer_enable_counter(TIM6); }
void sound_set_frequency(uint32_t freq) { uint32_t prescaler, period; if (freq <= 200) { // switch off pwm timer_disable_oc_output(TIM1, TIM_OC1); // return; } // reset TIMx peripheral timer_reset(TIM1); // roughly factor into 16-bit period = (rcc_timer_frequency / 1) / freq; prescaler = (period / 65536) + 1; period = (period / prescaler); // Set the timers global mode to: // - use no divider // - alignment edge // - count direction up timer_set_mode(TIM1, TIM_CR1_CKD_CK_INT, TIM_CR1_CMS_EDGE, TIM_CR1_DIR_UP); timer_set_prescaler(TIM1, prescaler - 1); timer_set_repetition_counter(TIM1, 0); timer_enable_preload(TIM1); timer_continuous_mode(TIM1); timer_set_period(TIM1, period - 1); // start with disabled pwm output timer_disable_oc_output(TIM1, TIM_OC1); // NOTE: on advanced timers as TIM1 we have // to break the main output, otherwise // no pwm output signal will be present on pin timer_enable_break_main_output(TIM1); // configure output mode timer_set_oc_mode(TIM1, TIM_OC1, TIM_OCM_PWM1); // set period for 50/50 duty cycle timer_set_oc_value(TIM1, TIM_OC1, period / 2); // enable pwm output timer_enable_oc_output(TIM1, TIM_OC1); // start timer timer_enable_counter(TIM1); }
void ppm_arch_init ( void ) { /* timer clock enable */ rcc_peripheral_enable_clock(PPM_RCC, PPM_PERIPHERAL); /* GPIOA clock enable */ rcc_peripheral_enable_clock(&RCC_APB2ENR, PPM_GPIO_PERIPHERAL); /* timer gpio configuration */ gpio_set_mode(PPM_GPIO_PORT, GPIO_MODE_INPUT, GPIO_CNF_INPUT_FLOAT, PPM_GPIO_PIN); /* Time Base configuration */ timer_reset(PPM_TIMER); timer_set_mode(PPM_TIMER, TIM_CR1_CKD_CK_INT, TIM_CR1_CMS_EDGE, TIM_CR1_DIR_UP); timer_set_period(PPM_TIMER, 0xFFFF); timer_set_prescaler(PPM_TIMER, 0x8); /* TIM2 configuration: Input Capture mode --------------------- The external signal is connected to TIM2 CH2 pin (PA.01) The Rising edge is used as active edge, ------------------------------------------------------------ */ timer_ic_set_polarity(PPM_TIMER, PPM_CHANNEL, TIM_IC_RISING); timer_ic_set_input(PPM_TIMER, PPM_CHANNEL, PPM_TIMER_INPUT); timer_ic_set_prescaler(PPM_TIMER, PPM_CHANNEL, TIM_IC_PSC_OFF); timer_ic_set_filter(PPM_TIMER, PPM_CHANNEL, TIM_IC_OFF); /* Enable timer Interrupt(s). */ nvic_set_priority(PPM_IRQ, 2); nvic_enable_irq(PPM_IRQ); #ifdef PPM_IRQ2 nvic_set_priority(PPM_IRQ2, 2); nvic_enable_irq(PPM_IRQ2); #endif /* Enable the CC2 and Update interrupt requests. */ timer_enable_irq(PPM_TIMER, PPM_IRQ_FLAGS); /* Enable capture channel. */ timer_ic_enable(PPM_TIMER, PPM_CHANNEL); /* TIM2 enable counter */ timer_enable_counter(PPM_TIMER); ppm_last_pulse_time = 0; ppm_cur_pulse = RADIO_CONTROL_NB_CHANNEL; timer_rollover_cnt = 0; }
/** * Setup the timer in 10Khz mode * This timer will be used to keep track of last poll time difference */ static void tim_setup(void) { uint32_t tick_freq = 10000; uint32_t timer_clock = rcc_apb1_frequency; if (rcc_ahb_frequency != rcc_apb1_frequency) { timer_clock *= 2; } uint32_t clock_div = timer_clock / tick_freq; timer_reset(TIM6); timer_set_prescaler(TIM6, clock_div - 1); timer_set_period(TIM6, 0xFFFF); timer_enable_counter(TIM6); }
void plc_wait_tmr_init(void) { //Wait timer config, basic timers TIM6 and TIM7 may be used rcc_periph_clock_enable( PLC_WAIT_TMR_PERIPH ); timer_reset ( PLC_WAIT_TMR ); timer_set_prescaler ( PLC_WAIT_TMR, ((2*rcc_apb1_frequency)/1000000ul - 1)); //1MHz timer_disable_preload ( PLC_WAIT_TMR ); timer_continuous_mode ( PLC_WAIT_TMR ); timer_set_period ( PLC_WAIT_TMR, 1000 ); //1KHz timer_enable_counter ( PLC_WAIT_TMR ); timer_enable_irq ( PLC_WAIT_TMR, TIM_DIER_UIE); nvic_enable_irq( PLC_WAIT_TMR_VECTOR ); }
int main(void) { int i; rcc_clock_setup_in_hse_8mhz_out_72mhz(); rcc_periph_clock_enable(RCC_GPIOC); rcc_periph_clock_enable(RCC_TIM3); rcc_periph_clock_enable(RCC_AFIO); gpio_primary_remap(0,AFIO_MAPR_TIM3_REMAP_FULL_REMAP ); gpio_set_mode(GPIOC, GPIO_MODE_OUTPUT_50_MHZ, GPIO_CNF_OUTPUT_ALTFN_PUSHPULL , GPIO9); timer_set_mode(TIM3, TIM_CR1_CKD_CK_INT, TIM_CR1_CMS_EDGE, TIM_CR1_DIR_UP); timer_set_prescaler(TIM3,36); timer_set_period(TIM3, 1000); timer_set_oc_mode(TIM3, TIM_OC4, TIM_OCM_PWM1); timer_enable_oc_output(TIM3, TIM_OC4); // timer_enable_preload(TIM3); //timer_continuous_mode(TIM3); timer_enable_counter(TIM3); #if defined(ENABLE_SEMIHOSTING) && (ENABLE_SEMIHOSTING) initialise_monitor_handles(); #endif uint16_t a = 0; while (1) { for(i=0; i< 1000; i++){ timer_set_oc_value(TIM3, TIM_OC4, i); delay(); } for(i=999; i >=0 ; i--){ timer_set_oc_value(TIM3, TIM_OC4, i); delay(); } //gpio_toggle(GPIOC, GPIO9); /* LED on/off */ //printf("hello world\n"); } }
static void platform_init_eventtimer() { /* Set up TIM2 as 32bit clock */ timer_reset(TIM2); timer_set_mode(TIM2, TIM_CR1_CKD_CK_INT, TIM_CR1_CMS_EDGE, TIM_CR1_DIR_UP); timer_set_period(TIM2, 0xFFFFFFFF); timer_set_prescaler(TIM2, 0); timer_disable_preload(TIM2); timer_continuous_mode(TIM2); /* Setup output compare registers */ timer_disable_oc_output(TIM2, TIM_OC1); timer_disable_oc_output(TIM2, TIM_OC2); timer_disable_oc_output(TIM2, TIM_OC3); timer_disable_oc_output(TIM2, TIM_OC4); timer_disable_oc_clear(TIM2, TIM_OC1); timer_disable_oc_preload(TIM2, TIM_OC1); timer_set_oc_slow_mode(TIM2, TIM_OC1); timer_set_oc_mode(TIM2, TIM_OC1, TIM_OCM_FROZEN); /* Setup input captures for CH2-4 Triggers */ gpio_mode_setup(GPIOB, GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO3); gpio_set_af(GPIOB, GPIO_AF1, GPIO3); timer_ic_set_input(TIM2, TIM_IC2, TIM_IC_IN_TI2); timer_ic_set_filter(TIM2, TIM_IC2, TIM_IC_CK_INT_N_2); timer_ic_set_polarity(TIM2, TIM_IC2, TIM_IC_FALLING); timer_ic_enable(TIM2, TIM_IC2); gpio_mode_setup(GPIOB, GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO10); gpio_set_af(GPIOB, GPIO_AF1, GPIO10); timer_ic_set_input(TIM2, TIM_IC3, TIM_IC_IN_TI3); timer_ic_set_filter(TIM2, TIM_IC3, TIM_IC_CK_INT_N_2); timer_ic_set_polarity(TIM2, TIM_IC3, TIM_IC_FALLING); timer_ic_enable(TIM2, TIM_IC3); gpio_mode_setup(GPIOB, GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO11); gpio_set_af(GPIOB, GPIO_AF1, GPIO11); timer_ic_set_input(TIM2, TIM_IC4, TIM_IC_IN_TI4); timer_ic_set_filter(TIM2, TIM_IC4, TIM_IC_CK_INT_N_2); timer_ic_set_polarity(TIM2, TIM_IC4, TIM_IC_FALLING); timer_ic_enable(TIM2, TIM_IC4); timer_enable_counter(TIM2); timer_enable_irq(TIM2, TIM_DIER_CC2IE); timer_enable_irq(TIM2, TIM_DIER_CC3IE); timer_enable_irq(TIM2, TIM_DIER_CC4IE); nvic_enable_irq(NVIC_TIM2_IRQ); nvic_set_priority(NVIC_TIM2_IRQ, 0); }
void delay_nus(sGrpDev* pGrpDev, uint32_t nCount) { volatile uint16_t TIMCounter = nCount; if (pGrpDev->pTimer) { /* Counter enable. */ /* Reset prescaler value. */ timer_set_prescaler(pGrpDev->pTimer, 72); timer_direction_down(pGrpDev->pTimer); timer_enable_counter(pGrpDev->pTimer); timer_set_counter(pGrpDev->pTimer, TIMCounter); /* Start timer. */ TIM_CR1(pGrpDev->pTimer) |= TIM_CR1_CEN; while (TIMCounter > 1) { TIMCounter = timer_get_counter(pGrpDev->pTimer); } timer_disable_counter(pGrpDev->pTimer); } }
void usbuart_init(void) { #if defined(BLACKMAGIC) /* On mini hardware, UART and SWD share connector pins. * Don't enable UART if we're being debugged. */ if ((platform_hwversion() == 1) && (SCS_DEMCR & SCS_DEMCR_TRCENA)) return; #endif rcc_peripheral_enable_clock(&USBUSART_APB_ENR, USBUSART_CLK_ENABLE); UART_PIN_SETUP(); /* Setup UART parameters. */ usart_set_baudrate(USBUSART, 38400); usart_set_databits(USBUSART, 8); usart_set_stopbits(USBUSART, USART_STOPBITS_1); usart_set_mode(USBUSART, USART_MODE_TX_RX); usart_set_parity(USBUSART, USART_PARITY_NONE); usart_set_flow_control(USBUSART, USART_FLOWCONTROL_NONE); /* Finally enable the USART. */ usart_enable(USBUSART); /* Enable interrupts */ USBUSART_CR1 |= USART_CR1_RXNEIE; nvic_set_priority(USBUSART_IRQ, IRQ_PRI_USBUSART); nvic_enable_irq(USBUSART_IRQ); /* Setup timer for running deferred FIFO processing */ USBUSART_TIM_CLK_EN(); timer_reset(USBUSART_TIM); timer_set_mode(USBUSART_TIM, TIM_CR1_CKD_CK_INT, TIM_CR1_CMS_EDGE, TIM_CR1_DIR_UP); timer_set_prescaler(USBUSART_TIM, rcc_ppre2_frequency / USBUART_TIMER_FREQ_HZ * 2 - 1); timer_set_period(USBUSART_TIM, USBUART_TIMER_FREQ_HZ / USBUART_RUN_FREQ_HZ - 1); /* Setup update interrupt in NVIC */ nvic_set_priority(USBUSART_TIM_IRQ, IRQ_PRI_USBUSART_TIM); nvic_enable_irq(USBUSART_TIM_IRQ); /* turn the timer on */ timer_enable_counter(USBUSART_TIM); }
void pwm_setup(void) { // Timer 5 rcc_peripheral_enable_clock(&RCC_APB1ENR, RCC_APB1ENR_TIM5EN); pwm_init(TIM5, 1, PWM_PERIOD); pwm_init(TIM5, 2, PWM_PERIOD); pwm_init(TIM5, 3, PWM_PERIOD); pwm_init(TIM5, 4, PWM_PERIOD); // LED channels = PA0..3 rcc_peripheral_enable_clock(&RCC_AHB1ENR, RCC_AHB1ENR_IOPAEN); gpio_mode_setup(GPIOA, GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO0 | GPIO1 | GPIO2 | GPIO3); // AF2 = TIM4_CH1..4 gpio_set_af(GPIOA, GPIO_AF2, GPIO0 | GPIO1 | GPIO2 | GPIO3); timer_enable_counter(TIM5); }
static int silence_nmea() { int attempt; size_t i; /* Configure the GPS */ for (attempt = 0; attempt < 4; attempt++) { calculate_crc_and_ack(set_port, sizeof(silence_nmea)); for (i = 0; i < sizeof(set_port); i++) usart_send_blocking(USART2, set_port[i]); timer_clear_flag(TIM5, TIM_SR_UIF); timer_set_counter(TIM5, 0); timer_enable_counter(TIM5); for (i = 0; i < sizeof(expect_ack); ) { while (!timer_get_flag(TIM5, TIM_SR_UIF) && !usart_get_flag(USART2, USART_SR_RXNE)); if (timer_get_flag(TIM5, TIM_SR_UIF)) break; if (expect_ack[i] == usart_recv(USART2)) i++; else i = 0; } timer_disable_counter(TIM5); if (i < sizeof(expect_ack)) continue; else break; } while (usart_get_flag(USART2, USART_SR_RXNE)) usart_recv(USART2); return attempt < 4; }
void timer_setup(void) { rcc_periph_clock_enable(RCC_TIM2); nvic_enable_irq(NVIC_TIM2_IRQ); nvic_set_priority(NVIC_TIM2_IRQ, 1); timer_reset(TIM2); /* Timer global mode: - No Divider, Alignment edge, Direction up */ timer_set_mode(TIM2, TIM_CR1_CKD_CK_INT, TIM_CR1_CMS_EDGE, TIM_CR1_DIR_UP); timer_continuous_mode(TIM2); /* Set timer prescaler. 72MHz/1440 => 50000 counts per second. */ timer_set_prescaler(TIM2, 1440); /* End timer value. When this is reached an interrupt is generated. */ timer_set_period(TIM2, BLINK_INTERVAL); /* Update interrupt enable. */ timer_enable_irq(TIM2, TIM_DIER_UIE); /* Start timer. */ timer_enable_counter(TIM2); }
static void timer_setup(void) { /* Set up the timer TIM2 for injected sampling */ uint32_t timer; timer = TIM2; rcc_periph_clock_enable(RCC_TIM2); /* Time Base configuration */ timer_reset(timer); timer_set_mode(timer, TIM_CR1_CKD_CK_INT, TIM_CR1_CMS_EDGE, TIM_CR1_DIR_UP); timer_set_period(timer, 0xFF); timer_set_prescaler(timer, 0x8); timer_set_clock_division(timer, 0x0); /* Generate TRGO on every update. */ timer_set_master_mode(timer, TIM_CR2_MMS_UPDATE); timer_enable_counter(timer); }
void delay_ms(sGrpDev* pGrpDev, uint32_t nCount) { volatile uint16_t TIMCounter;// = nCount; uint16_t cnt2; /* Counter enable. */ /* Reset prescaler value. */ timer_set_prescaler(pGrpDev->pTimer, 7200); timer_direction_down(pGrpDev->pTimer); timer_enable_counter(pGrpDev->pTimer); for (cnt2 = 0; cnt2 < 750; cnt2++) { TIMCounter = nCount; timer_set_counter(pGrpDev->pTimer, TIMCounter); /* Start timer. */ TIM_CR1(pGrpDev->pTimer) |= TIM_CR1_CEN; while (TIMCounter > 1) { TIMCounter = timer_get_counter(pGrpDev->pTimer); } } timer_disable_counter(pGrpDev->pTimer); }
void hbridge_init() { // M- bridge // A9 - pin 21 - PWM2A - HIN // B0 - pin 15 - PWM2B - \LIN // M+ bridge // A8 - pin 20 - PWM1A - HIN // A7 - pin 14 - PWM1B - \LIN rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_IOPAEN | RCC_APB2ENR_IOPBEN | RCC_APB2ENR_AFIOEN | RCC_APB2ENR_TIM1EN); AFIO_MAPR |= AFIO_MAPR_TIM1_REMAP_PARTIAL_REMAP; gpio_set_mode(GPIOA, GPIO_MODE_OUTPUT_50_MHZ, GPIO_CNF_OUTPUT_ALTFN_PUSHPULL, GPIO7 | GPIO8 | GPIO9); gpio_set_mode(GPIOB, GPIO_MODE_OUTPUT_50_MHZ, GPIO_CNF_OUTPUT_ALTFN_PUSHPULL, GPIO0); timer_reset(TIM1); timer_set_mode(TIM1, TIM_CR1_CKD_CK_INT, TIM_CR1_CMS_CENTER_1, TIM_CR1_DIR_UP); timer_set_period(TIM1, half_period_ticks); timer_set_prescaler(TIM1, 9); // / 10 timer_set_oc_mode(TIM1, TIM_OC1, TIM_OCM_PWM2); timer_set_oc_polarity_high(TIM1, TIM_OC1); timer_set_oc_polarity_low(TIM1, TIM_OC1N); timer_enable_oc_output(TIM1, TIM_OC1); timer_enable_oc_output(TIM1, TIM_OC1N); timer_set_oc_value(TIM1, TIM_OC1, half_period_ticks); timer_set_oc_mode(TIM1, TIM_OC2, TIM_OCM_PWM2); timer_set_oc_polarity_high(TIM1, TIM_OC2); timer_set_oc_polarity_low(TIM1, TIM_OC2N); timer_enable_oc_output(TIM1, TIM_OC2); timer_enable_oc_output(TIM1, TIM_OC2N); timer_set_oc_value(TIM1, TIM_OC2, half_period_ticks); timer_enable_break_main_output(TIM1); timer_enable_counter(TIM1); }
void BACKLIGHT_Brightness(u8 brightness) { timer_disable_counter(TIM3); if (brightness == 0) { // Turn off Backlight gpio_set_mode(GPIOB, GPIO_MODE_INPUT, GPIO_CNF_INPUT_FLOAT, GPIO1); } else if(brightness > 9) { // Turn on Backlight full gpio_set_mode(GPIOB, GPIO_MODE_OUTPUT_50_MHZ, GPIO_CNF_OUTPUT_PUSHPULL, GPIO1); gpio_set(GPIOB, GPIO1); } else { gpio_set_mode(GPIOB, GPIO_MODE_OUTPUT_50_MHZ, GPIO_CNF_OUTPUT_ALTFN_PUSHPULL, GPIO1); u32 duty_cycle = 720 * brightness / 10 ; timer_set_oc_value(TIM3, TIM_OC4, duty_cycle); timer_enable_counter(TIM3); } }
void freq_capture_setup(void) { /* Configure PE11 (AF1: TIM1_CH2) (SYNC_IN). */ rcc_peripheral_enable_clock(&RCC_AHB1ENR, RCC_AHB1ENR_IOPEEN); gpio_mode_setup(GPIOE, GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO11); gpio_set_af(GPIOE, GPIO_AF1, GPIO11); /* Timer1: Input compare */ /* Enable timer clock. */ rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_TIM1EN); /* Reset timer. */ timer_reset(TIM1); /* Configure timer1. */ timer_set_mode(TIM1, TIM_CR1_CKD_CK_INT, // Internal clock TIM_CR1_CMS_EDGE, // Edge synchronization TIM_CR1_DIR_UP); // Count upward timer_set_prescaler(TIM1, TIMER1_PRESCALER); timer_set_period(TIM1, TIMER1_PERIOD); //Sets TIM1_ARR timer_continuous_mode(TIM1); /* Configure PE13: Toggle pin on falling edge via interrupt */ //rcc_peripheral_enable_clock(&RCC_AHB1ENR, RCC_AHB1ENR_IOPEEN); //gpio_mode_setup(GPIOE, GPIO_MODE_OUTPUT, GPIO_PUPD_PULLDOWN, GPIO13); /* Configure input capture. */ timer_ic_disable(TIM1, TIM_IC2); timer_ic_set_polarity(TIM1, TIM_IC2, TIM_IC_RISING); timer_ic_set_prescaler(TIM1, TIM_IC2, TIM_IC_PSC_OFF); timer_ic_set_input(TIM1, TIM_IC2, TIM_IC_IN_TI2); // See RM, p. 561: digital filter //timer_ic_set_filter(TIM1, TIM_IC2, TIM_IC_DTF_DIV_32_N_8); timer_ic_set_filter(TIM1, TIM_IC2, TIM_IC_OFF); timer_ic_enable(TIM1, TIM_IC2); /* Enable counter. */ timer_enable_counter(TIM1); timer_clear_flag (TIM1, TIM_SR_CC2IF); /* Enable IRQs */ nvic_enable_irq(NVIC_TIM1_UP_TIM10_IRQ); timer_enable_irq(TIM1, TIM_DIER_UIE); nvic_enable_irq(NVIC_TIM1_CC_IRQ); timer_enable_irq(TIM1, TIM_DIER_CC2IE); }
static void platform_init_freqsensor(unsigned char pin) { uint32_t tim; switch(pin) { case 1: /* TIM1 CH1 */ tim = TIM1; gpio_mode_setup(GPIOA, GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO8); gpio_set_af(GPIOA, GPIO_AF1, GPIO8); break; }; timer_reset(tim); timer_set_mode(tim, TIM_CR1_CKD_CK_INT, TIM_CR1_CMS_EDGE, TIM_CR1_DIR_UP); timer_set_period(tim, 0xFFFFFFFF); timer_disable_preload(tim); timer_continuous_mode(tim); /* Setup output compare registers */ timer_disable_oc_output(tim, TIM_OC1); timer_disable_oc_output(tim, TIM_OC2); timer_disable_oc_output(tim, TIM_OC3); timer_disable_oc_output(tim, TIM_OC4); /* Set up compare */ timer_ic_set_input(tim, TIM_IC1, TIM_IC_IN_TI1); timer_ic_set_filter(tim, TIM_IC1, TIM_IC_CK_INT_N_8); timer_ic_set_polarity(tim, TIM_IC1, TIM_IC_RISING); timer_set_prescaler(tim, 2*SENSOR_FREQ_DIVIDER); /* Prescale set to map up to 20kHz */ timer_slave_set_mode(tim, TIM_SMCR_SMS_RM); timer_slave_set_trigger(tim, TIM_SMCR_TS_IT1FP1); timer_ic_enable(tim, TIM_IC1); timer_enable_counter(tim); timer_enable_irq(tim, TIM_DIER_CC1IE); switch(pin) { case 1: nvic_enable_irq(NVIC_TIM1_CC_IRQ); nvic_set_priority(NVIC_TIM1_CC_IRQ, 64); break; } }
/*--------------------------------------------------------------------*/ void timer_setup(void) { /* Enable TIM2 clock. */ rcc_periph_clock_enable(RCC_TIM2); timer_reset(TIM2); /* Timer global mode: - No divider, Alignment edge, Direction up */ timer_set_mode(TIM2, TIM_CR1_CKD_CK_INT, TIM_CR1_CMS_EDGE, TIM_CR1_DIR_UP); timer_continuous_mode(TIM2); timer_set_period(TIM2, 1000); timer_disable_oc_output(TIM2, TIM_OC2 | TIM_OC3 | TIM_OC4); timer_enable_oc_output(TIM2, TIM_OC1); timer_disable_oc_clear(TIM2, TIM_OC1); timer_disable_oc_preload(TIM2, TIM_OC1); timer_set_oc_slow_mode(TIM2, TIM_OC1); timer_set_oc_mode(TIM2, TIM_OC1, TIM_OCM_TOGGLE); timer_set_oc_value(TIM2, TIM_OC1, 500); timer_disable_preload(TIM2); /* Set the timer trigger output (for the DAC) to the channel 1 output compare */ timer_set_master_mode(TIM2, TIM_CR2_MMS_COMPARE_OC1REF); timer_enable_counter(TIM2); }
static void timer_setup(void) { /* Set up the timer TIM2 for injected sampling */ uint32_t timer; volatile uint32_t *rcc_apbenr; uint32_t rcc_apb; timer = TIM2; rcc_apbenr = &RCC_APB1ENR; rcc_apb = RCC_APB1ENR_TIM2EN; rcc_peripheral_enable_clock(rcc_apbenr, rcc_apb); /* Time Base configuration */ timer_reset(timer); timer_set_mode(timer, TIM_CR1_CKD_CK_INT, TIM_CR1_CMS_EDGE, TIM_CR1_DIR_UP); timer_set_period(timer, 0xFF); timer_set_prescaler(timer, 0x8); timer_set_clock_division(timer, 0x0); /* Generate TRGO on every update. */ timer_set_master_mode(timer, TIM_CR2_MMS_UPDATE); timer_enable_counter(timer); }
void ws2812_send( void ) { /* init the DMA data transfer */ dma_clear_interrupt_flags( DMA1, DMA_CHANNEL2, DMA_TEIF | DMA_HTIF | DMA_TCIF | DMA_GIF); dma_clear_interrupt_flags( DMA1, DMA_CHANNEL3, DMA_TEIF | DMA_HTIF | DMA_TCIF | DMA_GIF); dma_clear_interrupt_flags( DMA1, DMA_CHANNEL4, DMA_TEIF | DMA_HTIF | DMA_TCIF | DMA_GIF); dma_set_memory_address( DMA1, DMA_CHANNEL4, (uint32_t)actual_bitframe); dma_set_number_of_data( DMA1, DMA_CHANNEL2, WS2812_BUFFERSIZE); dma_set_number_of_data( DMA1, DMA_CHANNEL3, WS2812_BUFFERSIZE); dma_set_number_of_data( DMA1, DMA_CHANNEL4, WS2812_BUFFERSIZE); TIM3_SR = 0; dma_enable_channel( DMA1, DMA_CHANNEL2); dma_enable_channel( DMA1, DMA_CHANNEL3); dma_enable_channel( DMA1, DMA_CHANNEL4); //timer_enable_irq( TIM3, TIM_DIER_TDE); timer_enable_irq( TIM3, TIM_DIER_CC1DE); timer_enable_irq( TIM3, TIM_DIER_CC3DE); timer_enable_irq( TIM3, TIM_DIER_UDE); timer_set_counter(TIM3, 60); timer_enable_counter(TIM3); SCB_ICSR |= SCB_ICSR_PENDSVSET; }
int main (void) { clock_setup(); //setup the main clock for 168MHz usart_setup(); //setup usart1 for debug messages debug_send("\n\n\n*************************************\n"); debug_send("* Lynx test starting up *\n"); debug_send("* Waveforms *\n"); debug_send("* Joe Roberts *\n"); debug_send("* UROP - Summer 2013 *\n"); debug_send("*************************************\n\n\n"); debug_send("ledpins_setup()\n"); ledpins_setup(); //setup the status led's gpio's debug_send("dac_setup()\n"); dac_setup(); //setup the dac gpio's debug_send("transmit_timer_setup(1)\n"); transmit_timer_setup(1); //setup the transmit timer and its interrupt debug_send("Starting the transmission timer\n"); timer_enable_counter(TIM2); while(1) { usart_wait_recv_ready(USART2); timer_disable_counter(TIM2); timer_set_counter(TIM2, 0); char message = usart_recv_blocking(USART2); debug_send("\nRecieved "); usart_send_blocking(USART2, message); bool done = false; char param; while(!done) { debug_send(": Send your parameter [0-9]\n"); usart_wait_recv_ready(USART2); param = usart_recv_blocking(USART2); if((param>47)&&(param<58)) { done = true; param = param-48; //ASCII to number } else debug_send("\nParameter must be [0-9] - try again\n"); } if(message=='n') n = 1000*param; if(message=='t') { transmit_timer_setup(10*param); timer_enable_counter(TIM2); } if(message=='w') set_waveform(param); } debug_send("We somehow escaped the for ever loop\n"); debug_send("..This is a little sad, there's not much you can do to fix this\n\n\n\n"); debug_send("goodbye, cruel world"); while(1); return 1; }
void accel_highg_go() { timer_enable_counter(TIM1); }
static void timer_setup(void) { /* Enable TIM3 clock. */ rcc_periph_clock_enable(RCC_TIM3); timer_reset(TIM3); /* Timer global mode: - No divider, Alignment edge, Direction up */ timer_set_mode(TIM3, TIM_CR1_CKD_CK_INT,TIM_CR1_CMS_EDGE, TIM_CR1_DIR_UP); timer_continuous_mode(TIM3); timer_set_period(TIM3, PERIOD); timer_disable_preload(TIM3); /* prescaler F_SYS/48 = TIM3 clock is 1 MHz */ timer_set_prescaler(TIM3,48); //timer_disable_oc_output(TIM3, TIM_OC2 | TIM_OC3 | TIM_OC4); timer_enable_oc_output(TIM3, TIM_OC1); timer_disable_oc_output(TIM3,TIM_OC2); timer_enable_oc_output(TIM3, TIM_OC3); //timer_enable_oc_output(TIM3, TIM_OC4); // motor ch1 timer_set_oc_mode(TIM3, TIM_OC1, TIM_OCM_PWM1); // motor ch2 timer_set_oc_mode(TIM3, TIM_OC2, TIM_OCM_PWM1); // motor ch3 timer_set_oc_mode(TIM3, TIM_OC3, TIM_OCM_PWM1); // motor ch3 timer_set_oc_mode(TIM3, TIM_OC4, TIM_OCM_PWM1); /* disable preload */ timer_disable_oc_preload(TIM3, TIM_OC1); timer_disable_oc_preload(TIM3, TIM_OC2); timer_disable_oc_preload(TIM3, TIM_OC3); timer_disable_oc_preload(TIM3, TIM_OC4); /* polarity */ timer_set_oc_polarity_high(TIM3,TIM_OC1); timer_set_oc_polarity_high(TIM3,TIM_OC2); timer_set_oc_polarity_high(TIM3,TIM_OC3); timer_set_oc_polarity_high(TIM3,TIM_OC4); //timer_enable_oc_clear(TIM3, TIM_OC1); //timer_set_oc_slow_mode(TIM3, TIM_OC1); timer_set_oc_value(TIM3, TIM_OC1, PULSE); timer_set_oc_value(TIM3, TIM_OC2, PULSE*3); timer_set_oc_value(TIM3, TIM_OC3, PULSE*2); timer_set_oc_value(TIM3, TIM_OC4, PULSE*4); //timer_generate_event(TIM3,TIM_EGR_CC1G); //timer_enable_update_event(TIM3); nvic_enable_irq(NVIC_TIM3_IRQ); timer_enable_irq(TIM3,TIM_DIER_CC1IE); timer_enable_irq(TIM3,TIM_DIER_CC2IE); timer_enable_irq(TIM3,TIM_DIER_CC3IE); timer_enable_irq(TIM3,TIM_DIER_CC4IE); //timer_enable_irq(TIM3,TIM_DIER_CC2IE); timer_enable_irq(TIM3,TIM_DIER_UIE); /* Set the timer trigger output (for the DAC) to the channel 1 output compare */ //timer_set_master_mode(TIM3, TIM_CR2_MMS_COMPARE_OC1REF); timer_enable_counter(TIM3); }
void PID_tim_init(void) { /* Enable TIM1 clock. and Port E clock (for outputs) */ rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_TIM1EN); rcc_peripheral_enable_clock(&RCC_AHB1ENR, RCC_AHB1ENR_IOPEEN); //Set TIM1 channel (and complementary) output to alternate function push-pull'. //f4 TIM1=> GIO9: CH1, GPIO11: CH2, GPIO13: CH3 //f4 TIM1=> GIO8: CH1N, GPIO10: CH2N, GPIO12: CH3N gpio_mode_setup(GPIOE, GPIO_MODE_AF,GPIO_PUPD_NONE,GPIO9 | GPIO11 | GPIO13); gpio_set_af(GPIOE, GPIO_AF1, GPIO9 | GPIO11 | GPIO13); gpio_mode_setup(GPIOE, GPIO_MODE_AF,GPIO_PUPD_NONE,GPIO8 | GPIO10 | GPIO12); gpio_set_af(GPIOE, GPIO_AF1, GPIO8 | GPIO10 | GPIO12); /* Enable TIM1 commutation interrupt. */ //nvic_enable_irq(NVIC_TIM1_TRG_COM_TIM11_IRQ); //f4 /* Reset TIM1 peripheral. */ timer_reset(TIM1); /* Timer global mode: * - No divider * - Alignment edge * - Direction up */ timer_set_mode(TIM1, TIM_CR1_CKD_CK_INT, //For dead time and filter sampling, not important for now. TIM_CR1_CMS_CENTER_3, //TIM_CR1_CMS_EDGE //TIM_CR1_CMS_CENTER_1 //TIM_CR1_CMS_CENTER_2 //TIM_CR1_CMS_CENTER_3 la frequencia del pwm se divide a la mitad. (frecuencia senoidal) TIM_CR1_DIR_UP); timer_set_prescaler(TIM1, PRESCALE); //1 = disabled (max speed) timer_set_repetition_counter(TIM1, 0); //disabled timer_enable_preload(TIM1); timer_continuous_mode(TIM1); /* Period (32kHz). */ timer_set_period(TIM1, PWM_PERIOD_ARR); //ARR (value compared against main counter to reload counter aka: period of counter) /* Configure break and deadtime. */ //timer_set_deadtime(TIM1, deadtime_percentage*pwm_period_ARR); timer_set_enabled_off_state_in_idle_mode(TIM1); timer_set_enabled_off_state_in_run_mode(TIM1); timer_disable_break(TIM1); timer_set_break_polarity_high(TIM1); timer_disable_break_automatic_output(TIM1); timer_set_break_lock(TIM1, TIM_BDTR_LOCK_OFF); /* Disable outputs. */ timer_disable_oc_output(TIM1, TIM_OC1); timer_disable_oc_output(TIM1, TIM_OC1N); timer_disable_oc_output(TIM1, TIM_OC2); timer_disable_oc_output(TIM1, TIM_OC2N); timer_disable_oc_output(TIM1, TIM_OC3); timer_disable_oc_output(TIM1, TIM_OC3N); /* -- OC1 and OC1N configuration -- */ /* Configure global mode of line 1. */ timer_enable_oc_preload(TIM1, TIM_OC1); timer_set_oc_mode(TIM1, TIM_OC1, TIM_OCM_PWM1); /* Configure OC1. */ timer_set_oc_polarity_high(TIM1, TIM_OC1); timer_set_oc_idle_state_unset(TIM1, TIM_OC1); //When idle (braked) put 0 on output /* Configure OC1N. */ timer_set_oc_polarity_high(TIM1, TIM_OC1N); timer_set_oc_idle_state_unset(TIM1, TIM_OC1N); /* Set the capture compare value for OC1. */ timer_set_oc_value(TIM1, TIM_OC1, INIT_DUTY*PWM_PERIOD_ARR);//initial_duty_cycle*pwm_period_ARR); /* -- OC2 and OC2N configuration -- */ /* Configure global mode of line 2. */ timer_enable_oc_preload(TIM1, TIM_OC2); timer_set_oc_mode(TIM1, TIM_OC2, TIM_OCM_PWM1); /* Configure OC2. */ timer_set_oc_polarity_high(TIM1, TIM_OC2); timer_set_oc_idle_state_unset(TIM1, TIM_OC2); /* Configure OC2N. */ timer_set_oc_polarity_high(TIM1, TIM_OC2N); timer_set_oc_idle_state_unset(TIM1, TIM_OC2N); /* Set the capture compare value for OC2. */ timer_set_oc_value(TIM1, TIM_OC2, INIT_DUTY*PWM_PERIOD_ARR);//initial_duty_cycle*pwm_period_ARR); /* -- OC3 and OC3N configuration -- */ /* Configure global mode of line 3. */ timer_enable_oc_preload(TIM1, TIM_OC3); timer_set_oc_mode(TIM1, TIM_OC3, TIM_OCM_PWM1); /* Configure OC3. */ timer_set_oc_polarity_high(TIM1, TIM_OC3); timer_set_oc_idle_state_unset(TIM1, TIM_OC3); /* Configure OC3N. */ timer_set_oc_polarity_high(TIM1, TIM_OC3N); timer_set_oc_idle_state_unset(TIM1, TIM_OC3N); /* Set the capture compare value for OC3. */ timer_set_oc_value(TIM1, TIM_OC3, INIT_DUTY*PWM_PERIOD_ARR);//initial_duty_cycle*pwm_period_ARR);//100); /* Reenable outputs. */ timer_enable_oc_output(TIM1, TIM_OC1); timer_enable_oc_output(TIM1, TIM_OC1N); timer_enable_oc_output(TIM1, TIM_OC2); timer_enable_oc_output(TIM1, TIM_OC2N); timer_enable_oc_output(TIM1, TIM_OC3); timer_enable_oc_output(TIM1, TIM_OC3N); /* ---- */ /* ARR reload enable. */ timer_enable_preload(TIM1); /* * Enable preload of complementary channel configurations and * update on COM event. */ //timer_enable_preload_complementry_enable_bits(TIM1); timer_disable_preload_complementry_enable_bits(TIM1); /* Enable outputs in the break subsystem. */ timer_enable_break_main_output(TIM1); /* Generate update event to reload all registers before starting*/ timer_generate_event(TIM1, TIM_EGR_UG); /* Counter enable. */ timer_enable_counter(TIM1); /* Enable commutation interrupt. */ //timer_enable_irq(TIM1, TIM_DIER_COMIE); /*********/ /*Capture compare interrupt*/ //enable capture compare interrupt timer_enable_update_event(TIM1); /* Enable commutation interrupt. */ //timer_enable_irq(TIM1, TIM_DIER_CC1IE); //Capture/compare 1 interrupt enable /* Enable commutation interrupt. */ //timer_enable_irq(TIM1, TIM_DIER_CC1IE); timer_enable_irq(TIM1, TIM_DIER_UIE); nvic_enable_irq(NVIC_TIM1_UP_TIM10_IRQ); }
static void tim_setup(void) { /* Enable TIM2 clock. */ rcc_periph_clock_enable(RCC_TIM2); /* Enable TIM2 interrupt. */ nvic_enable_irq(NVIC_TIM2_IRQ); /* Reset TIM2 peripheral. */ timer_reset(TIM2); /* Timer global mode: * - No divider * - Alignment edge * - Direction up */ timer_set_mode(TIM2, TIM_CR1_CKD_CK_INT, TIM_CR1_CMS_EDGE, TIM_CR1_DIR_UP); /* Reset prescaler value. * Running the clock at 5kHz. */ /* * On STM32F4 the timers are not running directly from pure APB1 or * APB2 clock busses. The APB1 and APB2 clocks used for timers might * be the double of the APB1 and APB2 clocks. This depends on the * setting in DCKCFGR register. By default the behaviour is the * following: If the Prescaler APBx is greater than 1 the derived timer * APBx clocks will be double of the original APBx frequencies. Only if * the APBx prescaler is set to 1 the derived timer APBx will equal the * original APBx frequencies. * * In our case here the APB1 is devided by 4 system frequency and APB2 * divided by 2. This means APB1 timer will be 2 x APB1 and APB2 will * be 2 x APB2. So when we try to calculate the prescaler value we have * to use rcc_apb1_freqency * 2!!! * * For additional information see reference manual for the stm32f4 * familiy of chips. Page 204 and 213 */ timer_set_prescaler(TIM2, ((rcc_apb1_frequency * 2) / 10000)); /* Enable preload. */ timer_disable_preload(TIM2); /* Continous mode. */ timer_continuous_mode(TIM2); /* Period (36kHz). */ timer_set_period(TIM2, 65535); /* Disable outputs. */ timer_disable_oc_output(TIM2, TIM_OC1); timer_disable_oc_output(TIM2, TIM_OC2); timer_disable_oc_output(TIM2, TIM_OC3); timer_disable_oc_output(TIM2, TIM_OC4); /* -- OC1 configuration -- */ /* Configure global mode of line 1. */ timer_disable_oc_clear(TIM2, TIM_OC1); timer_disable_oc_preload(TIM2, TIM_OC1); timer_set_oc_slow_mode(TIM2, TIM_OC1); timer_set_oc_mode(TIM2, TIM_OC1, TIM_OCM_FROZEN); /* Set the capture compare value for OC1. */ timer_set_oc_value(TIM2, TIM_OC1, 1000); /* ---- */ /* ARR reload enable. */ timer_disable_preload(TIM2); /* Counter enable. */ timer_enable_counter(TIM2); /* Enable commutation interrupt. */ timer_enable_irq(TIM2, TIM_DIER_CC1IE); }
/** * Commutation timer hardware initialization. */ void comm_tim_init(void) { comm_tim_data.freq = 65535; (void)gpc_setup_reg(GPROT_COMM_TIM_FREQ_REG_ADDR, &(comm_tim_data.freq)); /* TIM2 clock enable */ rcc_peripheral_enable_clock(&RCC_APB1ENR, RCC_APB1ENR_TIM2EN); /* Enable the TIM2 gloabal interrupt. */ nvic_enable_irq(NVIC_TIM2_IRQ); /* Reset TIM2 peripheral. */ timer_reset(TIM2); /* TIM2 time base configuration */ timer_set_mode(TIM2, TIM_CR1_CKD_CK_INT, TIM_CR1_CMS_EDGE, TIM_CR1_DIR_UP); /* Set prescaler value */ timer_set_prescaler(TIM2, 4); /* Disable preload. */ timer_disable_preload(TIM2); /* Set continous mode. */ timer_continuous_mode(TIM2); /* Set period to maximum */ timer_set_period(TIM2, 65535); /* Disable outputs. */ timer_disable_oc_output(TIM2, TIM_OC1); timer_disable_oc_output(TIM2, TIM_OC2); timer_disable_oc_output(TIM2, TIM_OC3); timer_disable_oc_output(TIM2, TIM_OC4); /* TIM2 Output Compare Timing Mode configuration: Channel1 */ timer_disable_oc_clear(TIM2, TIM_OC1); timer_disable_oc_preload(TIM2, TIM_OC1); timer_set_oc_slow_mode(TIM2, TIM_OC1); timer_set_oc_mode(TIM2, TIM_OC1, TIM_OCM_FROZEN); //timer_set_oc_polarity_high(TIM2, TIM_OC1); /* Set initial capture compare value for OC1 */ timer_set_oc_value(TIM2, TIM_OC1, comm_tim_data.freq); /* ARR reload enable */ timer_disable_preload(TIM2); /* Counter enable */ timer_enable_counter(TIM2); /* TIM2 Capture Compare 1 IT enable */ timer_enable_irq(TIM2, TIM_DIER_CC1IE); /* TIM2 Update IT enable */ timer_enable_irq(TIM2, TIM_DIER_UIE); comm_tim_reset(); }
void motor_TIMER_config(void) { timer_period = rcc_ppre1_frequency / 5000; timer_reset(TIM3); /* set timer mode no divider ; alignment on edge ; direction up */ timer_set_mode(TIM3, TIM_CR1_CKD_CK_INT, TIM_CR1_CMS_EDGE, TIM_CR1_DIR_UP); timer_continuous_mode(TIM3); /* Period (5kHz). TIM3 clk source is APB1*/ timer_set_period(TIM3, timer_period); /* Reset prescaler value. */ timer_set_prescaler(TIM3, 0); motor_front_left = 0; motor_rear_left = 0; motor_front_rigth = 0; motor_rear_rigth = 0; /************ channels configuration ************/ timer_disable_oc_output(TIM3, MOTOR_PWM_REAR_LEFT); timer_disable_oc_output(TIM3, MOTOR_PWM_FRONT_LEFT); timer_disable_oc_output(TIM3, MOTOR_PWM_REAR_RIGHT); timer_disable_oc_output(TIM3, MOTOR_PWM_FRONT_RIGHT); //configure OCx line timer_set_oc_slow_mode(TIM3, MOTOR_PWM_REAR_LEFT); timer_set_oc_slow_mode(TIM3, MOTOR_PWM_FRONT_LEFT); timer_set_oc_slow_mode(TIM3, MOTOR_PWM_REAR_RIGHT); timer_set_oc_slow_mode(TIM3, MOTOR_PWM_FRONT_RIGHT); timer_set_oc_mode(TIM3, MOTOR_PWM_REAR_LEFT, TIM_OCM_PWM1); timer_set_oc_mode(TIM3, MOTOR_PWM_FRONT_LEFT, TIM_OCM_PWM1); timer_set_oc_mode(TIM3, MOTOR_PWM_REAR_RIGHT, TIM_OCM_PWM1); timer_set_oc_mode(TIM3, MOTOR_PWM_FRONT_RIGHT, TIM_OCM_PWM1); //configure OCx output timer_set_oc_polarity_high(TIM3, MOTOR_PWM_REAR_LEFT); timer_set_oc_polarity_high(TIM3, MOTOR_PWM_FRONT_LEFT); timer_set_oc_polarity_high(TIM3, MOTOR_PWM_REAR_RIGHT); timer_set_oc_polarity_high(TIM3, MOTOR_PWM_FRONT_RIGHT); timer_set_oc_idle_state_set(TIM3, MOTOR_PWM_REAR_LEFT); timer_set_oc_idle_state_set(TIM3, MOTOR_PWM_FRONT_LEFT); timer_set_oc_idle_state_set(TIM3, MOTOR_PWM_REAR_RIGHT); timer_set_oc_idle_state_set(TIM3, MOTOR_PWM_FRONT_RIGHT); /* Set the capture compare value */ timer_set_oc_value(TIM3, MOTOR_PWM_FRONT_LEFT, motor_front_left); timer_set_oc_value(TIM3, MOTOR_PWM_REAR_LEFT, motor_rear_left); timer_set_oc_value(TIM3, MOTOR_PWM_FRONT_RIGHT, motor_front_rigth); timer_set_oc_value(TIM3, MOTOR_PWM_REAR_RIGHT, motor_rear_rigth); timer_enable_oc_output(TIM3, MOTOR_PWM_REAR_LEFT); timer_enable_oc_output(TIM3, MOTOR_PWM_FRONT_LEFT); timer_enable_oc_output(TIM3, MOTOR_PWM_REAR_RIGHT); timer_enable_oc_output(TIM3, MOTOR_PWM_FRONT_RIGHT); timer_enable_counter(TIM3); }
void PulseWidth::start_timer() { timer_enable_counter(timer_peripheral); }
void actuators_pwm_arch_init(void) { /*----------------------------------- * Configure timer peripheral clocks *-----------------------------------*/ /* TIM3, TIM4 and TIM5 clock enable */ rcc_peripheral_enable_clock(&RCC_APB1ENR, RCC_APB1ENR_TIM3EN); #if REMAP_SERVOS_5AND6 rcc_peripheral_enable_clock(&RCC_APB1ENR, RCC_APB1ENR_TIM5EN); #else rcc_peripheral_enable_clock(&RCC_APB1ENR, RCC_APB1ENR_TIM4EN); #endif #if USE_SERVOS_7AND8 rcc_peripheral_enable_clock(&RCC_APB1ENR, RCC_APB1ENR_TIM4EN); #endif /*---------------- * Configure GPIO *----------------*/ /* GPIO A,B and C clock enable */ rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_IOPAEN | RCC_APB2ENR_IOPBEN | RCC_APB2ENR_IOPCEN | RCC_APB2ENR_AFIOEN); /* TIM3 GPIO for PWM1..4 */ AFIO_MAPR |= AFIO_MAPR_TIM3_REMAP_FULL_REMAP; gpio_set_mode(GPIO_BANK_TIM3_FR, GPIO_MODE_OUTPUT_50_MHZ, GPIO_CNF_OUTPUT_ALTFN_PUSHPULL, GPIO_TIM3_FR_CH1 | GPIO_TIM3_FR_CH2 | GPIO_TIM3_FR_CH3 | GPIO_TIM3_FR_CH4); /* TIM4 GPIO for PWM7..8 */ #if USE_SERVOS_7AND8 gpio_set_mode(GPIO_BANK_TIM4, GPIO_MODE_OUTPUT_50_MHZ, GPIO_CNF_OUTPUT_ALTFN_PUSHPULL, GPIO_TIM4_CH1 | GPIO_TIM4_CH2); #endif /* TIM4/5 GPIO for PWM6..7 */ #if REMAP_SERVOS_5AND6 gpio_set_mode(GPIO_BANK_TIM5, GPIO_MODE_OUTPUT_50_MHZ, GPIO_CNF_OUTPUT_ALTFN_PUSHPULL, GPIO_TIM5_CH1 | GPIO_TIM5_CH2); #else gpio_set_mode(GPIO_BANK_TIM4, GPIO_MODE_OUTPUT_50_MHZ, GPIO_CNF_OUTPUT_ALTFN_PUSHPULL, GPIO_TIM4_CH3 | GPIO_TIM4_CH4); #endif /*--------------- * Timer 3 setup *---------------*/ timer_reset(TIM3); /* Timer global mode: * - No divider. * - Alignement edge. * - Direction up. */ timer_set_mode(TIM3, TIM_CR1_CKD_CK_INT, TIM_CR1_CMS_EDGE, TIM_CR1_DIR_UP); timer_set_prescaler(TIM3, (PCLK / ONE_MHZ_CLK) - 1); // 1uS timer_disable_preload(TIM3); timer_continuous_mode(TIM3); timer_set_period(TIM3, (ONE_MHZ_CLK / SERVO_HZ) - 1); /* Disable outputs. */ timer_disable_oc_output(TIM3, TIM_OC1); timer_disable_oc_output(TIM3, TIM_OC2); timer_disable_oc_output(TIM3, TIM_OC3); timer_disable_oc_output(TIM3, TIM_OC4); /* -- Channel configuration -- */ actuators_pwm_arch_channel_init(TIM3, TIM_OC1); actuators_pwm_arch_channel_init(TIM3, TIM_OC2); actuators_pwm_arch_channel_init(TIM3, TIM_OC3); actuators_pwm_arch_channel_init(TIM3, TIM_OC4); /* * Set initial output compare values. * Note: Maybe we should preload the compare registers with some sensible * values before we enable the timer? */ //timer_set_oc_value(TIM3, TIM_OC1, 1000); //timer_set_oc_value(TIM3, TIM_OC2, 1000); //timer_set_oc_value(TIM3, TIM_OC3, 1000); //timer_set_oc_value(TIM3, TIM_OC4, 1000); /* -- Enable timer -- */ /* * ARR reload enable. * Note: In our case it does not matter much if we do preload or not. As it * is unlikely we will want to change the frequency of the timer during * runtime anyways. */ timer_enable_preload(TIM3); /* Counter enable. */ timer_enable_counter(TIM3); #if (!REMAP_SERVOS_5AND6 || USE_SERVOS_7AND8) #if !REMAP_SERVOS_5AND6 #pragma message "Not remapping servos 5 and 6 using PB8 and PB9 -> TIM4" #endif #if USE_SERVOS_7AND8 #pragma message "Enabeling sevros 7 and 8 on PB6, PB7 -> TIM4" #endif /*--------------- * Timer 4 setup *---------------*/ timer_reset(TIM4); /* Timer global mode: * - No divider. * - Alignement edge. * - Direction up. */ timer_set_mode(TIM4, TIM_CR1_CKD_CK_INT, TIM_CR1_CMS_EDGE, TIM_CR1_DIR_UP); timer_set_prescaler(TIM4, (PCLK / ONE_MHZ_CLK) - 1); // 1uS timer_disable_preload(TIM4); timer_continuous_mode(TIM4); #ifdef SERVO_HZ_SECONDARY timer_set_period(TIM4, (ONE_MHZ_CLK / SERVO_HZ_SECONDARY) - 1); #else timer_set_period(TIM4, (ONE_MHZ_CLK / SERVO_HZ) - 1); #endif /* Disable outputs. */ #if USE_SERVOS_7AND8 timer_disable_oc_output(TIM4, TIM_OC1); timer_disable_oc_output(TIM4, TIM_OC2); #endif #if !REMAP_SERVOS_5AND6 timer_disable_oc_output(TIM4, TIM_OC3); timer_disable_oc_output(TIM4, TIM_OC4); #endif /* -- Channel configuration -- */ #if USE_SERVOS_7AND8 actuators_pwm_arch_channel_init(TIM4, TIM_OC1); actuators_pwm_arch_channel_init(TIM4, TIM_OC2); #endif #if !REMAP_SERVOS_5AND6 actuators_pwm_arch_channel_init(TIM4, TIM_OC3); actuators_pwm_arch_channel_init(TIM4, TIM_OC4); #endif /* * Set initial output compare values. * Note: Maybe we should preload the compare registers with some sensible * values before we enable the timer? */ #if USE_SERVOS_7AND8 //timer_set_oc_value(TIM4, TIM_OC1, 1000); //timer_set_oc_value(TIM4, TIM_OC2, 1000); #endif #if ! REMAP_SERVOS_5AND6 //timer_set_oc_value(TIM4, TIM_OC3, 1000); //timer_set_oc_value(TIM4, TIM_OC4, 1000); #endif /* -- Enable timer -- */ /* * ARR reload enable. * Note: In our case it does not matter much if we do preload or not. As it * is unlikely we will want to change the frequency of the timer during * runtime anyways. */ timer_enable_preload(TIM4); /* Counter enable. */ timer_enable_counter(TIM4); #endif #if REMAP_SERVOS_5AND6 #pragma message "Remapping servo outputs 5 and 6 to PA0,PA1 -> TIM5" /*--------------- * Timer 5 setup *---------------*/ timer_reset(TIM5); /* Timer global mode: * - No divider. * - Alignement edge. * - Direction up. */ timer_set_mode(TIM5, TIM_CR1_CKD_CK_INT, TIM_CR1_CMS_EDGE, TIM_CR1_DIR_UP); timer_set_prescaler(TIM5, (PCLK / ONE_MHZ_CLK) - 1); // 1uS timer_disable_preload(TIM5); timer_continuous_mode(TIM5); #ifdef SERVO_HZ_SECONDARY timer_set_period(TIM5, (ONE_MHZ_CLK / SERVO_HZ_SECONDARY) - 1); #else timer_set_period(TIM5, (ONE_MHZ_CLK / SERVO_HZ) - 1); #endif /* Disable outputs. */ timer_disable_oc_output(TIM5, TIM_OC1); timer_disable_oc_output(TIM5, TIM_OC2); /* -- Channel configuration -- */ actuators_pwm_arch_channel_init(TIM5, TIM_OC1); actuators_pwm_arch_channel_init(TIM5, TIM_OC2); /* * Set the capture compare value for OC1. * Note: Maybe we should preload the compare registers with some sensible * values before we enable the timer? */ //timer_set_oc_value(TIM5, TIM_OC1, 1000); //timer_set_oc_value(TIM5, TIM_OC2, 1000); /* -- Enable timer -- */ /* * ARR reload enable. * Note: In our case it does not matter much if we do preload or not. As it * is unlikely we will want to change the frequency of the timer during * runtime anyways. */ timer_enable_preload(TIM5); /* Counter enable. */ timer_enable_counter(TIM5); #endif }