static void s390_cpu_initfn(Object *obj)
{
CPUState *cs = CPU(obj);
S390CPU *cpu = S390_CPU(obj);
CPUS390XState *env = &cpu->env;
static bool inited;
static int cpu_num = 0;
#if !defined(CONFIG_USER_ONLY)
struct tm tm;
#endif
cs->env_ptr = env;
cpu_exec_init(env);
#if !defined(CONFIG_USER_ONLY)
qemu_register_reset(s390_cpu_machine_reset_cb, cpu);
qemu_get_timedate(&tm, 0);
env->tod_offset = TOD_UNIX_EPOCH +
(time2tod(mktimegm(&tm)) * 1000000000ULL);
env->tod_basetime = 0;
env->tod_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, s390x_tod_timer, cpu);
env->cpu_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, s390x_cpu_timer, cpu);
s390_cpu_set_state(CPU_STATE_STOPPED, cpu);
#endif
env->cpu_num = cpu_num++;
if (tcg_enabled() && !inited) {
inited = true;
s390x_translate_init();
}
}
static void s390_cpu_initfn(Object *obj)
{
CPUState *cs = CPU(obj);
S390CPU *cpu = S390_CPU(obj);
CPUS390XState *env = &cpu->env;
static bool inited;
#if !defined(CONFIG_USER_ONLY)
struct tm tm;
#endif
cs->env_ptr = env;
cs->halted = 1;
cs->exception_index = EXCP_HLT;
object_property_add(OBJECT(cpu), "id", "int64_t", s390x_cpu_get_id,
s390x_cpu_set_id, NULL, NULL, NULL);
s390_cpu_model_register_props(obj);
#if !defined(CONFIG_USER_ONLY)
qemu_get_timedate(&tm, 0);
env->tod_offset = TOD_UNIX_EPOCH +
(time2tod(mktimegm(&tm)) * 1000000000ULL);
env->tod_basetime = 0;
env->tod_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, s390x_tod_timer, cpu);
env->cpu_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, s390x_cpu_timer, cpu);
s390_cpu_set_state(CPU_STATE_STOPPED, cpu);
#endif
if (tcg_enabled() && !inited) {
inited = true;
s390x_translate_init();
}
}
static void s390_cpu_initfn(Object *obj)
{
CPUState *cs = CPU(obj);
S390CPU *cpu = S390_CPU(obj);
CPUS390XState *env = &cpu->env;
static bool inited;
static int cpu_num = 0;
#if !defined(CONFIG_USER_ONLY)
struct tm tm;
#endif
cs->env_ptr = env;
cpu_exec_init(env);
#if !defined(CONFIG_USER_ONLY)
qemu_register_reset(s390_cpu_machine_reset_cb, cpu);
qemu_get_timedate(&tm, 0);
env->tod_offset = TOD_UNIX_EPOCH +
(time2tod(mktimegm(&tm)) * 1000000000ULL);
env->tod_basetime = 0;
env->tod_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, s390x_tod_timer, cpu);
env->cpu_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, s390x_cpu_timer, cpu);
/* set CPUState::halted state to 1 to avoid decrementing the running
* cpu counter in s390_cpu_reset to a negative number at
* initial ipl */
cs->halted = 1;
#endif
env->cpu_num = cpu_num++;
env->ext_index = -1;
if (tcg_enabled() && !inited) {
inited = true;
s390x_translate_init();
}
}
static void rtc_realizefn(DeviceState *dev, Error **errp)
{
ISADevice *isadev = ISA_DEVICE(dev);
RTCState *s = MC146818_RTC(dev);
int base = 0x70;
s->cmos_data[RTC_REG_A] = 0x26;
s->cmos_data[RTC_REG_B] = 0x02;
s->cmos_data[RTC_REG_C] = 0x00;
s->cmos_data[RTC_REG_D] = 0x80;
/* This is for historical reasons. The default base year qdev property
* was set to 2000 for most machine types before the century byte was
* implemented.
*
* This if statement means that the century byte will be always 0
* (at least until 2079...) for base_year = 1980, but will be set
* correctly for base_year = 2000.
*/
if (s->base_year == 2000) {
s->base_year = 0;
}
rtc_set_date_from_host(isadev);
#ifdef TARGET_I386
switch (s->lost_tick_policy) {
case LOST_TICK_POLICY_SLEW:
s->coalesced_timer =
timer_new_ns(rtc_clock, rtc_coalesced_timer, s);
break;
case LOST_TICK_POLICY_DISCARD:
break;
default:
error_setg(errp, "Invalid lost tick policy.");
return;
}
#endif
s->periodic_timer = timer_new_ns(rtc_clock, rtc_periodic_timer, s);
s->update_timer = timer_new_ns(rtc_clock, rtc_update_timer, s);
check_update_timer(s);
s->clock_reset_notifier.notify = rtc_notify_clock_reset;
qemu_clock_register_reset_notifier(rtc_clock,
&s->clock_reset_notifier);
s->suspend_notifier.notify = rtc_notify_suspend;
qemu_register_suspend_notifier(&s->suspend_notifier);
memory_region_init_io(&s->io, OBJECT(s), &cmos_ops, s, "rtc", 2);
isa_register_ioport(isadev, &s->io, base);
qdev_set_legacy_instance_id(dev, base, 3);
qemu_register_reset(rtc_reset, s);
object_property_add(OBJECT(s), "date", "struct tm",
rtc_get_date, NULL, NULL, s, NULL);
}
/* To be called first on the ThrottleState */
void throttle_init(ThrottleState *ts,
QEMUClockType clock_type,
QEMUTimerCB *read_timer_cb,
QEMUTimerCB *write_timer_cb,
void *timer_opaque)
{
memset(ts, 0, sizeof(ThrottleState));
ts->clock_type = clock_type;
ts->timers[0] = timer_new_ns(clock_type, read_timer_cb, timer_opaque);
ts->timers[1] = timer_new_ns(clock_type, write_timer_cb, timer_opaque);
}
static void tusb6010_realize(DeviceState *dev, Error **errp)
{
TUSBState *s = TUSB(dev);
SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
s->otg_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, tusb_otg_tick, s);
s->pwr_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, tusb_power_tick, s);
memory_region_init_io(&s->iomem[1], OBJECT(s), &tusb_async_ops, s,
"tusb-async", UINT32_MAX);
sysbus_init_mmio(sbd, &s->iomem[0]);
sysbus_init_mmio(sbd, &s->iomem[1]);
sysbus_init_irq(sbd, &s->irq);
qdev_init_gpio_in(dev, tusb6010_irq, musb_irq_max + 1);
s->musb = musb_init(dev, 1);
}
static int vhost_vsock_load(QEMUFile *f, void *opaque, size_t size)
{
VHostVSock *vsock = opaque;
VirtIODevice *vdev = VIRTIO_DEVICE(vsock);
int ret;
ret = virtio_load(vdev, f, VHOST_VSOCK_SAVEVM_VERSION);
if (ret) {
return ret;
}
if (virtio_queue_get_addr(vdev, 2)) {
/* Defer transport reset event to a vm clock timer so that virtqueue
* changes happen after migration has completed.
*/
assert(!vsock->post_load_timer);
vsock->post_load_timer =
timer_new_ns(QEMU_CLOCK_VIRTUAL,
vhost_vsock_post_load_timer_cb,
vsock);
timer_mod(vsock->post_load_timer, 1);
}
return 0;
}
static void ipmi_bmc_extern_init(Object *obj)
{
IPMIBmcExtern *ibe = IPMI_BMC_EXTERN(obj);
ibe->extern_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, extern_timeout, ibe);
vmstate_register(NULL, 0, &vmstate_ipmi_bmc_extern, ibe);
}
void dp83932_init(NICInfo *nd, hwaddr base, int it_shift,
MemoryRegion *address_space,
qemu_irq irq, void* mem_opaque,
void (*memory_rw)(void *opaque, hwaddr addr, uint8_t *buf, int len, int is_write))
{
dp8393xState *s;
qemu_check_nic_model(nd, "dp83932");
s = g_malloc0(sizeof(dp8393xState));
s->address_space = address_space;
s->mem_opaque = mem_opaque;
s->memory_rw = memory_rw;
s->it_shift = it_shift;
s->irq = irq;
s->watchdog = timer_new_ns(QEMU_CLOCK_VIRTUAL, dp8393x_watchdog, s);
s->regs[SONIC_SR] = 0x0004; /* only revision recognized by Linux */
s->conf.macaddr = nd->macaddr;
s->conf.peers.ncs[0] = nd->netdev;
s->nic = qemu_new_nic(&net_dp83932_info, &s->conf, nd->model, nd->name, s);
qemu_format_nic_info_str(qemu_get_queue(s->nic), s->conf.macaddr.a);
qemu_register_reset(nic_reset, s);
nic_reset(s);
memory_region_init_io(&s->mmio, NULL, &dp8393x_ops, s,
"dp8393x", 0x40 << it_shift);
memory_region_add_subregion(address_space, base, &s->mmio);
}
static void wdt_diag288_realize(DeviceState *dev, Error **errp)
{
DIAG288State *diag288 = DIAG288(dev);
diag288->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, diag288_timer_expired,
dev);
}
static void arm_mptimer_realize(DeviceState *dev, Error **errp)
{
SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
ARMMPTimerState *s = ARM_MPTIMER(dev);
int i;
if (s->num_cpu < 1 || s->num_cpu > ARM_MPTIMER_MAX_CPUS) {
hw_error("%s: num-cpu must be between 1 and %d\n",
__func__, ARM_MPTIMER_MAX_CPUS);
}
/* We implement one timer block per CPU, and expose multiple MMIO regions:
* * region 0 is "timer for this core"
* * region 1 is "timer for core 0"
* * region 2 is "timer for core 1"
* and so on.
* The outgoing interrupt lines are
* * timer for core 0
* * timer for core 1
* and so on.
*/
for (i = 0; i < s->num_cpu; i++) {
TimerBlock *tb = &s->timerblock[i];
tb->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, timerblock_tick, tb);
sysbus_init_irq(sbd, &tb->irq);
memory_region_init_io(&tb->iomem, OBJECT(s), &timerblock_ops, tb,
"arm_mptimer_timerblock", 0x20);
sysbus_init_mmio(sbd, &tb->iomem);
}
}
static int tusb6010_init(SysBusDevice *sbd)
{
DeviceState *dev = DEVICE(sbd);
TUSBState *s = TUSB(dev);
s->otg_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, tusb_otg_tick, s);
s->pwr_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, tusb_power_tick, s);
memory_region_init_io(&s->iomem[1], OBJECT(s), &tusb_async_ops, s,
"tusb-async", UINT32_MAX);
sysbus_init_mmio(sbd, &s->iomem[0]);
sysbus_init_mmio(sbd, &s->iomem[1]);
sysbus_init_irq(sbd, &s->irq);
qdev_init_gpio_in(dev, tusb6010_irq, musb_irq_max + 1);
s->musb = musb_init(dev, 1);
return 0;
}
static int arm_mptimer_init(SysBusDevice *dev)
{
ARMMPTimerState *s = ARM_MPTIMER(dev);
int i;
if (s->num_cpu < 1 || s->num_cpu > MAX_CPUS) {
hw_error("%s: num-cpu must be between 1 and %d\n", __func__, MAX_CPUS);
}
/* We implement one timer block per CPU, and expose multiple MMIO regions:
* * region 0 is "timer for this core"
* * region 1 is "timer for core 0"
* * region 2 is "timer for core 1"
* and so on.
* The outgoing interrupt lines are
* * timer for core 0
* * timer for core 1
* and so on.
*/
memory_region_init_io(&s->iomem, OBJECT(s), &arm_thistimer_ops, s,
"arm_mptimer_timer", 0x20);
sysbus_init_mmio(dev, &s->iomem);
for (i = 0; i < s->num_cpu; i++) {
TimerBlock *tb = &s->timerblock[i];
tb->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, timerblock_tick, tb);
sysbus_init_irq(dev, &tb->irq);
memory_region_init_io(&tb->iomem, OBJECT(s), &timerblock_ops, tb,
"arm_mptimer_timerblock", 0x20);
sysbus_init_mmio(dev, &tb->iomem);
}
return 0;
}
/*
* Initialize clock mechanism.
*/
void cpu_riscv_clock_init (CPURISCVState *env)
{
env->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, &riscv_timer_cb, env);
env->csr[NEW_CSR_MTIMECMP] = 0;
cpu_riscv_store_timew(env, 1);
written_delta = 0;
instret_delta = 0;
}
void acpi_pm_tmr_init(ACPIREGS *ar, acpi_update_sci_fn update_sci,
MemoryRegion *parent)
{
ar->tmr.update_sci = update_sci;
ar->tmr.timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, acpi_pm_tmr_timer, ar);
memory_region_init_io(&ar->tmr.io, memory_region_owner(parent),
&acpi_pm_tmr_ops, ar, "acpi-tmr", 4);
memory_region_add_subregion(parent, 8, &ar->tmr.io);
}
void cpu_openrisc_clock_init(OpenRISCCPU *cpu)
{
cpu->env.timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, &openrisc_timer_cb, cpu);
cpu->env.ttmr = 0x00000000;
if (or1k_timer == NULL) {
or1k_timer = g_new0(OR1KTimerState, 1);
vmstate_register(NULL, 0, &vmstate_or1k_timer, or1k_timer);
}
}
static void aspeed_wdt_realize(DeviceState *dev, Error **errp)
{
SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
AspeedWDTState *s = ASPEED_WDT(dev);
s->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, aspeed_wdt_timer_expired,
dev);
memory_region_init_io(&s->iomem, OBJECT(s), &aspeed_wdt_ops, s,
TYPE_ASPEED_WDT, WDT_IO_REGION_SIZE);
sysbus_init_mmio(sbd, &s->iomem);
}
static void stm32f2xx_timer_init(Object *obj)
{
STM32F2XXTimerState *s = STM32F2XXTIMER(obj);
sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->irq);
memory_region_init_io(&s->iomem, obj, &stm32f2xx_timer_ops, s,
"stm32f2xx_timer", 0x4000);
sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->iomem);
s->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, stm32f2xx_timer_interrupt, s);
}
void hid_set_next_idle(HIDState *hs)
{
if (hs->idle) {
uint64_t expire_time = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) +
get_ticks_per_sec() * hs->idle * 4 / 1000;
if (!hs->idle_timer) {
hs->idle_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, hid_idle_timer, hs);
}
timer_mod_ns(hs->idle_timer, expire_time);
} else {
hid_del_idle_timer(hs);
}
}
static void i6300esb_realize(PCIDevice *dev, Error **errp)
{
I6300State *d = WATCHDOG_I6300ESB_DEVICE(dev);
i6300esb_debug("I6300State = %p\n", d);
d->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, i6300esb_timer_expired, d);
d->previous_reboot_flag = 0;
memory_region_init_io(&d->io_mem, OBJECT(d), &i6300esb_ops, d,
"i6300esb", 0x10);
pci_register_bar(&d->dev, 0, 0, &d->io_mem);
/* qemu_register_coalesced_mmio (addr, 0x10); ? */
}
static void cadence_uart_realize(DeviceState *dev, Error **errp)
{
CadenceUARTState *s = CADENCE_UART(dev);
s->fifo_trigger_handle = timer_new_ns(QEMU_CLOCK_VIRTUAL,
fifo_trigger_update, s);
/* FIXME use a qdev chardev prop instead of qemu_char_get_next_serial() */
s->chr = qemu_char_get_next_serial();
if (s->chr) {
qemu_chr_add_handlers(s->chr, uart_can_receive, uart_receive,
uart_event, s);
}
}
void configure_icount(const char *option)
{
vmstate_register(NULL, 0, &vmstate_timers, &timers_state);
if (!option) {
return;
}
icount_warp_timer = timer_new_ns(QEMU_CLOCK_REALTIME,
icount_warp_rt, NULL);
if (strcmp(option, "auto") != 0) {
icount_time_shift = strtol(option, NULL, 0);
use_icount = 1;
return;
}
use_icount = 2;
/* 125MIPS seems a reasonable initial guess at the guest speed.
It will be corrected fairly quickly anyway. */
icount_time_shift = 3;
/* Have both realtime and virtual time triggers for speed adjustment.
The realtime trigger catches emulated time passing too slowly,
the virtual time trigger catches emulated time passing too fast.
Realtime triggers occur even when idle, so use them less frequently
than VM triggers. */
icount_rt_timer = timer_new_ms(QEMU_CLOCK_REALTIME,
icount_adjust_rt, NULL);
timer_mod(icount_rt_timer,
qemu_clock_get_ms(QEMU_CLOCK_REALTIME) + 1000);
icount_vm_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL,
icount_adjust_vm, NULL);
timer_mod(icount_vm_timer,
qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) +
get_ticks_per_sec() / 10);
}
static void pl031_init(Object *obj)
{
PL031State *s = PL031(obj);
SysBusDevice *dev = SYS_BUS_DEVICE(obj);
struct tm tm;
memory_region_init_io(&s->iomem, obj, &pl031_ops, s, "pl031", 0x1000);
sysbus_init_mmio(dev, &s->iomem);
sysbus_init_irq(dev, &s->irq);
qemu_get_timedate(&tm, 0);
s->tick_offset = mktimegm(&tm) -
qemu_clock_get_ns(rtc_clock) / NANOSECONDS_PER_SECOND;
s->timer = timer_new_ns(rtc_clock, pl031_interrupt, s);
}
static int i6300esb_init(PCIDevice *dev)
{
I6300State *d = DO_UPCAST(I6300State, dev, dev);
i6300esb_debug("I6300State = %p\n", d);
d->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, i6300esb_timer_expired, d);
d->previous_reboot_flag = 0;
memory_region_init_io(&d->io_mem, OBJECT(d), &i6300esb_ops, d,
"i6300esb", 0x10);
pci_register_bar(&d->dev, 0, 0, &d->io_mem);
/* qemu_register_coalesced_mmio (addr, 0x10); ? */
return 0;
}
static CPUTimer *cpu_timer_create(const char *name, SPARCCPU *cpu,
QEMUBHFunc *cb, uint32_t frequency,
uint64_t disabled_mask)
{
CPUTimer *timer = g_malloc0(sizeof (CPUTimer));
timer->name = name;
timer->frequency = frequency;
timer->disabled_mask = disabled_mask;
timer->disabled = 1;
timer->clock_offset = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
timer->qtimer = timer_new_ns(QEMU_CLOCK_VIRTUAL, cb, cpu);
return timer;
}
static CharDriverState *chr_baum_init(const char *id,
ChardevBackend *backend,
ChardevReturn *ret,
bool *be_opened,
Error **errp)
{
ChardevCommon *common = backend->u.braille.data;
BaumDriverState *baum;
CharDriverState *chr;
brlapi_handle_t *handle;
chr = qemu_chr_alloc(common, errp);
if (!chr) {
return NULL;
}
baum = g_malloc0(sizeof(BaumDriverState));
baum->chr = chr;
chr->opaque = baum;
chr->chr_write = baum_write;
chr->chr_accept_input = baum_accept_input;
chr->chr_free = baum_free;
handle = g_malloc0(brlapi_getHandleSize());
baum->brlapi = handle;
baum->brlapi_fd = brlapi__openConnection(handle, NULL, NULL);
if (baum->brlapi_fd == -1) {
error_setg(errp, "brlapi__openConnection: %s",
brlapi_strerror(brlapi_error_location()));
goto fail_handle;
}
baum->deferred_init = 0;
baum->cellCount_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, baum_cellCount_timer_cb, baum);
qemu_set_fd_handler(baum->brlapi_fd, baum_chr_read, NULL, baum);
return chr;
fail_handle:
g_free(handle);
g_free(chr);
g_free(baum);
return NULL;
}
/* TODO: take a functional-clock argument */
struct soc_dma_s *soc_dma_init(int n)
{
int i;
struct dma_s *s = g_malloc0(sizeof(*s) + n * sizeof(*s->ch));
s->chnum = n;
s->soc.ch = s->ch;
for (i = 0; i < n; i ++) {
s->ch[i].dma = &s->soc;
s->ch[i].num = i;
s->ch[i].timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, soc_dma_ch_run, &s->ch[i]);
}
soc_dma_reset(&s->soc);
fifo_size = 0;
return &s->soc;
}
MIPSGICTimerState *mips_gictimer_init(void *opaque, uint32_t nvps,
MIPSGICTimerCB *cb)
{
int i;
MIPSGICTimerState *gictimer = g_new(MIPSGICTimerState, 1);
gictimer->vptimers = g_new(MIPSGICTimerVPState, nvps);
gictimer->countstop = 1;
gictimer->num_vps = nvps;
gictimer->opaque = opaque;
gictimer->cb = cb;
for (i = 0; i < nvps; i++) {
gictimer->vptimers[i].gictimer = gictimer;
gictimer->vptimers[i].vp_index = i;
gictimer->vptimers[i].qtimer = timer_new_ns(QEMU_CLOCK_VIRTUAL,
&gic_vptimer_cb,
&gictimer->vptimers[i]);
}
return gictimer;
}
CharDriverState *uart_hci_init(qemu_irq wakeup)
{
struct csrhci_s *s = (struct csrhci_s *)
g_malloc0(sizeof(struct csrhci_s));
s->chr.opaque = s;
s->chr.chr_write = csrhci_write;
s->chr.chr_ioctl = csrhci_ioctl;
s->chr.avail_connections = 1;
s->hci = qemu_next_hci();
s->hci->opaque = s;
s->hci->evt_recv = csrhci_out_hci_packet_event;
s->hci->acl_recv = csrhci_out_hci_packet_acl;
s->out_tm = timer_new_ns(QEMU_CLOCK_VIRTUAL, csrhci_out_tick, s);
s->pins = qemu_allocate_irqs(csrhci_pins, s, __csrhci_pins);
csrhci_reset(s);
return &s->chr;
}
static int cadence_uart_init(SysBusDevice *dev)
{
UartState *s = CADENCE_UART(dev);
memory_region_init_io(&s->iomem, OBJECT(s), &uart_ops, s, "uart", 0x1000);
sysbus_init_mmio(dev, &s->iomem);
sysbus_init_irq(dev, &s->irq);
s->fifo_trigger_handle = timer_new_ns(QEMU_CLOCK_VIRTUAL,
(QEMUTimerCB *)fifo_trigger_update, s);
s->char_tx_time = (get_ticks_per_sec() / 9600) * 10;
s->chr = qemu_char_get_next_serial();
if (s->chr) {
qemu_chr_add_handlers(s->chr, uart_can_receive, uart_receive,
uart_event, s);
}
return 0;
}
