static READ8_HANDLER( exidy_shriot_r ) { /* I/O is done if A2 == 0 */ if ((offset & 0x04) == 0) { switch (offset & 0x03) { case 0x00: /* port A */ return riot_porta_data; case 0x01: /* port A DDR */ return riot_porta_ddr; case 0x02: /* port B */ if (has_tms5220) { riot_portb_data &= ~0x0c; if (!tms5220_ready_r()) riot_portb_data |= 0x04; if (!tms5220_int_r()) riot_portb_data |= 0x08; } return riot_portb_data; case 0x03: /* port B DDR */ return riot_portb_ddr; } } /* interrupt flags are read if A2 == 1 and A0 == 1 */ else if (offset & 0x01) { int temp = riot_irq_flag; riot_irq_flag = 0; riot_irq_state = 0; update_irq_state(0); return temp; } /* timer count is read if A2 == 1 and A0 == 0 */ else { /* set the enable from the offset */ riot_timer_irq_enable = offset & 0x08; /* compute the timer based on the current state */ switch (riot_state) { case RIOT_IDLE: return 0x00; case RIOT_COUNT: return attotime_to_double(timer_timeleft(riot_timer)) * SH6532_CLOCK / riot_clock_divisor; case RIOT_POST_COUNT: return attotime_to_double(timer_timeleft(riot_timer)) * SH6532_CLOCK; } } logerror("Undeclared RIOT read: %x PC:%x\n",offset,activecpu_get_pc()); return 0xff; }
int z80ctc_r (int which, int ch) { z80ctc *ctc = ctcs + which; int mode; /* keep channel within range */ ch &= 3; mode = ctc->mode[ch]; /* if we're in counter mode, just return the count */ if ((mode & MODE) == MODE_COUNTER) return ctc->down[ch]; /* else compute the down counter value */ else { double clock = ((mode & PRESCALER) == PRESCALER_16) ? ctc->invclock16 : ctc->invclock256; if(errorlog) fprintf(errorlog,"CTC clock %f\n",1.0/clock); if (ctc->timer[ch]) return ((int)(timer_timeleft (ctc->timer[ch]) / clock) + 1) & 0xff; else return 0; } }
INLINE UINT8 get_timer(riot6532_state *riot) { /* if idle, return 0 */ if (riot->timerstate == TIMER_IDLE) return 0; /* if counting, return the number of ticks remaining */ else if (riot->timerstate == TIMER_COUNTING) return attotime_to_ticks(timer_timeleft(riot->timer), riot->device->clock) >> riot->timershift; /* if finishing, return the number of ticks without the shift */ else return attotime_to_ticks(timer_timeleft(riot->timer), riot->device->clock);
UINT16 via6522_device::get_counter1_value() { UINT16 val; if(m_t1_active) { val = time_to_cycles(timer_timeleft(m_t1)) - IFR_DELAY; } else { val = 0xffff - time_to_cycles(attotime_sub(timer_get_time(&m_machine), m_time1)); } return val; }
UINT8 z80ctc_r(int which, int ch) { z80ctc *ctc = ctcs + which; /* if we're in counter mode, just return the count */ if ((ctc->mode[ch] & MODE) == MODE_COUNTER) return ctc->down[ch]; /* else compute the down counter value */ else { double clock = ((ctc->mode[ch] & PRESCALER) == PRESCALER_16) ? ctc->invclock16 : ctc->invclock256; VPRINTF(("CTC clock %f\n",1.0/clock)); if (ctc->timer[ch]) return ((int)(timer_timeleft(ctc->timer[ch]) / clock) + 1) & 0xff; else return 0; } }
int via_read(int which, int offset) { struct via6522 *v = via + which; int val = 0; offset &= 0xf; switch (offset) { case VIA_PB: /* update the input */ if (PB_LATCH_ENABLE(v->acr) == 0) if (v->intf->in_b_func) v->in_b = v->intf->in_b_func(0); CLR_PB_INT(v); /* combine input and output values, hold DDRB bit 7 high if T1_SET_PB7 */ if (T1_SET_PB7(v->acr)) val = (v->out_b & (v->ddr_b | 0x80)) | (v->in_b & ~(v->ddr_b | 0x80)); else val = (v->out_b & v->ddr_b) + (v->in_b & ~v->ddr_b); break; case VIA_PA: /* update the input */ if (PA_LATCH_ENABLE(v->acr) == 0) if (v->intf->in_a_func) v->in_a = v->intf->in_a_func(0); /* combine input and output values */ val = (v->out_a & v->ddr_a) + (v->in_a & ~v->ddr_a); CLR_PA_INT(v); /* If CA2 is configured as output and in pulse or handshake mode, CA2 is set now */ if (CA2_AUTO_HS(v->pcr)) { if (v->out_ca2) { /* set CA2 */ v->out_ca2 = 0; /* call the CA2 output function */ if (v->intf->out_ca2_func) v->intf->out_ca2_func(0, 0); } } break; case VIA_PANH: /* update the input */ if (PA_LATCH_ENABLE(v->acr) == 0) if (v->intf->in_a_func) v->in_a = v->intf->in_a_func(0); /* combine input and output values */ val = (v->out_a & v->ddr_a) + (v->in_a & ~v->ddr_a); break; case VIA_DDRB: val = v->ddr_b; break; case VIA_DDRA: val = v->ddr_a; break; case VIA_T1CL: via_clear_int (v, INT_T1); if (v->t1) val = V_TIME_TO_CYCLES(timer_timeleft(v->t1)) & 0xff; else { if ( T1_CONTINUOUS(v->acr) ) { val = (TIMER1_VALUE(v)- (V_TIME_TO_CYCLES(timer_get_time()-v->time1) %TIMER1_VALUE(v))-1)&0xff; } else { val = (0x10000- (V_TIME_TO_CYCLES(timer_get_time()-v->time1)&0xffff) -1)&0xff; } } break; case VIA_T1CH: if (v->t1) val = V_TIME_TO_CYCLES(timer_timeleft(v->t1)) >> 8; else { if ( T1_CONTINUOUS(v->acr) ) { val = (TIMER1_VALUE(v)- (V_TIME_TO_CYCLES(timer_get_time()-v->time1) %TIMER1_VALUE(v))-1)>>8; } else {
attotime timer_device_timeleft(const device_config *timer) { timer_state *state = get_safe_token(timer); return timer_timeleft(state->timer); }
static int timer_running(ttl74123_t *chip) { return (attotime_compare(timer_timeleft(chip->timer), attotime_zero) > 0) && (attotime_compare(timer_timeleft(chip->timer), attotime_never) != 0); }
int riot_r(int chip, int offset) { int data = 0xff; offset&=0xf; if (!(offset&4)) { /* io part of chip */ switch( offset&3 ) { case 0: /* Data register A */ if( riot[chip].config->port_a.input ) data = (*riot[chip].config->port_a.input)(chip); /* mask input bits and combine with output bits */ data = (data & ~riot[chip].port_a.ddr) | (riot[chip].port_a.out & riot[chip].port_a.ddr); LOG(("riot(%d) DRA read : $%02x\n", chip, data)); break; case 1: /* Data direction register A */ data = riot[chip].port_a.ddr; LOG(("riot(%d) DDRA read : $%02x\n", chip, data)); break; case 2: /* Data register B */ if( riot[chip].config->port_b.input ) data = (*riot[chip].config->port_b.input)(chip); /* mask input bits and combine with output bits */ data = (data & ~riot[chip].port_b.ddr) | (riot[chip].port_b.out & riot[chip].port_b.ddr); /* LOG(("riot(%d) DRB read : $%02x\n", chip, data)); */ break; case 3: /* Data direction register B */ data = riot[chip].port_b.ddr; LOG(("riot(%d) DDRB read : $%02x\n", chip, data)); break; } } else { /* timer part of chip */ switch (offset&1) { case 0: /* Timer count read */ switch (riot[chip].state) { case Delay1: if (riot[chip].timer) data = (int)(timer_timeleft(riot[chip].timer)*riot[chip].config->baseclock); break; case Delay8: if (riot[chip].timer) data = (int)(timer_timeleft(riot[chip].timer)*riot[chip].config->baseclock)>>3; break; case Delay64: if (riot[chip].timer) data = (int)(timer_timeleft(riot[chip].timer)*riot[chip].config->baseclock)>>6; break; case Delay1024: if (riot[chip].timer) data = (int)(timer_timeleft(riot[chip].timer)*riot[chip].config->baseclock)>>10; break; case TimerShot: data=255-(int)((timer_get_time()-riot[chip].shottime)*riot[chip].config->baseclock); if (data <0 ) data=0; break; } if( riot[chip].irqen&&riot[chip].irq ) /* with IRQ? */ { if( riot[chip].config->irq_callback ) (*riot[chip].config->irq_callback)(chip, 0); } riot[chip].irq=0; break; case 1: /* Timer status read */ data = riot[chip].irq?0x80:0; LOG(("riot(%d) STAT read : $%02x%s\n", chip, data, (char*)((offset & 8) ? " (IRQ)":" "))); break; } /* problem when restarting with read the timer!? */ riot[chip].irqen = (offset & 8) ? 1 : 0; } return data; }
int ttl74123_device::timer_running() { return (attotime_compare(timer_timeleft(m_timer), attotime_zero) > 0) && (attotime_compare(timer_timeleft(m_timer), attotime_never) != 0); }
attotime timer_device_timeleft(running_device *timer) { timer_state *state = get_safe_token(timer); return timer_timeleft(state->timer); }
INLINE int m6530_r(int chip, int offset) { int data = 0xff; switch (offset) { case 0x00: case 0x08: /* Data register A */ if (chip == 1) { int which = ((m6530[1].drob & m6530[1].ddrb) >> 1) & 0x0f; switch (which) { case 0: /* key row 1 */ m6530[1].dria = input_port_0_r(0); logerror("read keybd(%d): %c%c%c%c%c%c%c\n", which, (m6530[1].dria & 0x40) ? '.' : '0', (m6530[1].dria & 0x20) ? '.' : '1', (m6530[1].dria & 0x10) ? '.' : '2', (m6530[1].dria & 0x08) ? '.' : '3', (m6530[1].dria & 0x04) ? '.' : '4', (m6530[1].dria & 0x02) ? '.' : '5', (m6530[1].dria & 0x01) ? '.' : '6'); break; case 1: /* key row 2 */ m6530[1].dria = input_port_1_r(0); logerror("read keybd(%d): %c%c%c%c%c%c%c\n", which, (m6530[1].dria & 0x40) ? '.' : '7', (m6530[1].dria & 0x20) ? '.' : '8', (m6530[1].dria & 0x10) ? '.' : '9', (m6530[1].dria & 0x08) ? '.' : 'A', (m6530[1].dria & 0x04) ? '.' : 'B', (m6530[1].dria & 0x02) ? '.' : 'C', (m6530[1].dria & 0x01) ? '.' : 'D'); break; case 2: /* key row 3 */ m6530[1].dria = input_port_2_r(0); logerror("read keybd(%d): %c%c%c%c%c%c%c\n", which, (m6530[1].dria & 0x40) ? '.' : 'E', (m6530[1].dria & 0x20) ? '.' : 'F', (m6530[1].dria & 0x10) ? '.' : 'a', (m6530[1].dria & 0x08) ? '.' : 'd', (m6530[1].dria & 0x04) ? '.' : '+', (m6530[1].dria & 0x02) ? '.' : 'g', (m6530[1].dria & 0x01) ? '.' : 'p'); break; case 3: /* WR4?? */ m6530[1].dria = 0xff; break; default: m6530[1].dria = 0xff; logerror("read DRA(%d) $ff\n", which); } } data = (m6530[chip].dria & ~m6530[chip].ddra) | (m6530[chip].droa & m6530[chip].ddra); logerror("m6530(%d) DRA read : $%02x\n", chip, data); break; case 0x01: case 0x09: /* Data direction register A */ data = m6530[chip].ddra; logerror("m6530(%d) DDRA read : $%02x\n", chip, data); break; case 0x02: case 0x0a: /* Data register B */ data = (m6530[chip].drib & ~m6530[chip].ddrb) | (m6530[chip].drob & m6530[chip].ddrb); logerror("m6530(%d) DRB read : $%02x\n", chip, data); break; case 0x03: case 0x0b: /* Data direction register B */ data = m6530[chip].ddrb; logerror("m6530(%d) DDRB read : $%02x\n", chip, data); break; case 0x04: case 0x0c: /* Timer count read (not supported?) */ data = (int) (256 * timer_timeleft(m6530[chip].timer) / TIME_IN_HZ(m6530[chip].clock)); m6530[chip].irqen = (offset & 8) ? 1 : 0; logerror("m6530(%d) TIMR read : $%02x%s\n", chip, data, (offset & 8) ? " (IRQ)" : ""); break; case 0x05: case 0x0d: /* Timer count read (not supported?) */ data = (int) (256 * timer_timeleft(m6530[chip].timer) / TIME_IN_HZ(m6530[chip].clock)); m6530[chip].irqen = (offset & 8) ? 1 : 0; logerror("m6530(%d) TIMR read : $%02x%s\n", chip, data, (offset & 8) ? " (IRQ)" : ""); break; case 0x06: case 0x0e: /* Timer count read */ data = (int) (256 * timer_timeleft(m6530[chip].timer) / TIME_IN_HZ(m6530[chip].clock)); m6530[chip].irqen = (offset & 8) ? 1 : 0; logerror("m6530(%d) TIMR read : $%02x%s\n", chip, data, (offset & 8) ? " (IRQ)" : ""); break; case 0x07: case 0x0f: /* Timer status read */ data = m6530[chip].state; m6530[chip].state &= ~0x80; m6530[chip].irqen = (offset & 8) ? 1 : 0; logerror("m6530(%d) STAT read : $%02x%s\n", chip, data, (offset & 8) ? " (IRQ)" : ""); break; }
get_timer - return the current timer value -------------------------------------------------*/ INLINE UINT8 get_timer(riot6532_state *riot) { /* if idle, return 0 */ if (riot->timerstate == TIMER_IDLE) return 0; /* if counting, return the number of ticks remaining */ else if (riot->timerstate == TIMER_COUNTING) return attotime_to_ticks(timer_timeleft(riot->timer), riot->device->clock) >> riot->timershift; /* if finishing, return the number of ticks without the shift */ else return attotime_to_ticks(timer_timeleft(riot->timer), riot->device->clock); } /*************************************************************************** INTERNAL FUNCTIONS ***************************************************************************/ /*------------------------------------------------- timer_end_callback - callback to process the timer -------------------------------------------------*/ static TIMER_CALLBACK( timer_end_callback ) {