/* Entry from the mainboard. */
void romstage_common(struct romstage_params *params)
{
struct chipset_power_state *ps;
int prev_sleep_state;
timestamp_add_now(TS_BEFORE_INITRAM);
ps = fill_power_state();
prev_sleep_state = chipset_prev_sleep_state(ps);
printk(BIOS_DEBUG, "prev_sleep_state = S%d\n", prev_sleep_state);
#if IS_ENABLED(CONFIG_ELOG_BOOT_COUNT)
if (prev_sleep_state != ACPI_S3)
boot_count_increment();
#endif
/* Initialize RAM */
raminit(params->mrc_params, prev_sleep_state);
timestamp_add_now(TS_AFTER_INITRAM);
romstage_handoff_init(prev_sleep_state == ACPI_S3);
}
void main(void)
{
timestamp_add_now(TS_START_ROMSTAGE);
console_init();
configure_l2ctlr();
tsadc_init();
/* vdd_log 1200mv is enough for ddr run 666Mhz */
regulate_vdd_log(1200);
timestamp_add_now(TS_BEFORE_INITRAM);
sdram_init(get_sdram_config());
timestamp_add_now(TS_AFTER_INITRAM);
/* Now that DRAM is up, add mappings for it and DMA coherency buffer. */
mmu_config_range((uintptr_t)_dram/MiB,
sdram_size_mb(), DCACHE_WRITEBACK);
mmu_config_range((uintptr_t)_dma_coherent/MiB,
_dma_coherent_size/MiB, DCACHE_OFF);
cbmem_initialize_empty();
timestamp_add_now(TS_END_ROMSTAGE);
run_ramstage();
}
/* Entry from the mainboard. */
void romstage_common(struct romstage_params *params)
{
struct romstage_handoff *handoff;
struct chipset_power_state *ps;
int prev_sleep_state;
timestamp_add_now(TS_BEFORE_INITRAM);
ps = fill_power_state();
prev_sleep_state = chipset_prev_sleep_state(ps);
printk(BIOS_DEBUG, "prev_sleep_state = S%d\n", prev_sleep_state);
#if CONFIG_ELOG_BOOT_COUNT
if (prev_sleep_state != 3)
boot_count_increment();
#endif
/* Initialize RAM */
raminit(params->mrc_params, prev_sleep_state);
timestamp_add_now(TS_AFTER_INITRAM);
handoff = romstage_handoff_find_or_add();
if (handoff != NULL)
handoff->s3_resume = (prev_sleep_state == 3);
else
printk(BIOS_DEBUG, "Romstage handoff structure not added!\n");
if (CONFIG_LPC_TPM) {
init_tpm(prev_sleep_state == 3);
}
}
void fsp_notify(u32 phase)
{
FSP_NOTIFY_PHASE notify_phase_proc;
NOTIFY_PHASE_PARAMS notify_phase_params;
EFI_STATUS status;
FSP_INFO_HEADER *fsp_header_ptr;
fsp_header_ptr = fsp_get_fih();
if (fsp_header_ptr == NULL) {
fsp_header_ptr = (void *)find_fsp(CONFIG_FSP_LOC);
if ((u32)fsp_header_ptr < 0xff) {
/* output something in case there is no serial */
post_code(0x4F);
die("Can't find the FSP!\n");
}
}
/* call FSP PEI to Notify PostPciEnumeration */
notify_phase_proc = (FSP_NOTIFY_PHASE)(fsp_header_ptr->ImageBase +
fsp_header_ptr->NotifyPhaseEntryOffset);
notify_phase_params.Phase = phase;
timestamp_add_now(phase == EnumInitPhaseReadyToBoot ?
TS_FSP_BEFORE_FINALIZE : TS_FSP_BEFORE_ENUMERATE);
status = notify_phase_proc(¬ify_phase_params);
timestamp_add_now(phase == EnumInitPhaseReadyToBoot ?
TS_FSP_AFTER_FINALIZE : TS_FSP_AFTER_ENUMERATE);
if (status != 0)
printk(BIOS_ERR, "FSP API NotifyPhase failed for phase 0x%x with status: 0x%x\n",
phase, status);
}
static void do_fsp_memory_init(struct fsp_header *hdr, bool s3wake,
const struct memranges *memmap)
{
uint32_t status;
fsp_memory_init_fn fsp_raminit;
FSPM_UPD fspm_upd, *upd;
FSPM_ARCH_UPD *arch_upd;
uint32_t fsp_version;
post_code(POST_MEM_PREINIT_PREP_START);
fsp_version = fsp_memory_settings_version(hdr);
upd = (FSPM_UPD *)(hdr->cfg_region_offset + hdr->image_base);
if (upd->FspUpdHeader.Signature != FSPM_UPD_SIGNATURE)
die("Invalid FSPM signature!\n");
/* Copy the default values from the UPD area */
memcpy(&fspm_upd, upd, sizeof(fspm_upd));
arch_upd = &fspm_upd.FspmArchUpd;
/* Reserve enough memory under TOLUD to save CBMEM header */
arch_upd->BootLoaderTolumSize = cbmem_overhead_size();
/* Fill common settings on behalf of chipset. */
if (fsp_fill_common_arch_params(arch_upd, s3wake, fsp_version,
memmap) != CB_SUCCESS)
die("FSPM_ARCH_UPD not found!\n");
/* Give SoC and mainboard a chance to update the UPD */
platform_fsp_memory_init_params_cb(&fspm_upd, fsp_version);
if (CONFIG(MMA))
setup_mma(&fspm_upd.FspmConfig);
post_code(POST_MEM_PREINIT_PREP_END);
/* Call FspMemoryInit */
fsp_raminit = (void *)(hdr->image_base + hdr->memory_init_entry_offset);
fsp_debug_before_memory_init(fsp_raminit, upd, &fspm_upd);
post_code(POST_FSP_MEMORY_INIT);
timestamp_add_now(TS_FSP_MEMORY_INIT_START);
status = fsp_raminit(&fspm_upd, fsp_get_hob_list_ptr());
post_code(POST_FSP_MEMORY_EXIT);
timestamp_add_now(TS_FSP_MEMORY_INIT_END);
fsp_debug_after_memory_init(status);
/* Handle any errors returned by FspMemoryInit */
fsp_handle_reset(status);
if (status != FSP_SUCCESS) {
printk(BIOS_CRIT, "FspMemoryInit returned 0x%08x\n", status);
die("FspMemoryInit returned an error!\n");
}
do_fsp_post_memory_init(s3wake, fsp_version);
}
void FspNotify (u32 Phase)
{
FSP_NOTFY_PHASE NotifyPhaseProc;
NOTIFY_PHASE_PARAMS NotifyPhaseParams;
EFI_STATUS Status;
if (fsp_header_ptr == NULL) {
fsp_header_ptr = (void *)find_fsp();
if ((u32)fsp_header_ptr < 0xff) {
post_code(0x4F); /* output something in case there is no serial */
die("Can't find the FSP!\n");
}
}
/* call FSP PEI to Notify PostPciEnumeration */
NotifyPhaseProc = (FSP_NOTFY_PHASE)(fsp_header_ptr->ImageBase +
fsp_header_ptr->NotifyPhaseEntry);
NotifyPhaseParams.Phase = Phase;
timestamp_add_now(Phase == EnumInitPhaseReadyToBoot ?
TS_FSP_BEFORE_FINALIZE : TS_FSP_BEFORE_ENUMERATE);
Status = NotifyPhaseProc (&NotifyPhaseParams);
timestamp_add_now(Phase == EnumInitPhaseReadyToBoot ?
TS_FSP_AFTER_FINALIZE : TS_FSP_AFTER_ENUMERATE);
if (Status != 0)
printk(BIOS_ERR,"FSP API NotifyPhase failed for phase 0x%x with status: 0x%x\n", Phase, Status);
}
static enum fsp_status do_silicon_init(struct fsp_header *hdr)
{
struct FSPS_UPD upd, *supd;
fsp_silicon_init_fn silicon_init;
enum fsp_status status;
supd = (struct FSPS_UPD *) (hdr->cfg_region_offset + hdr->image_base);
if (supd->FspUpdHeader.Signature != FSPS_UPD_SIGNATURE) {
printk(BIOS_ERR, "Invalid FSPS signature\n");
return FSP_INCOMPATIBLE_VERSION;
}
memcpy(&upd, supd, sizeof(upd));
/* Give SoC/mainboard a chance to populate entries */
platform_fsp_silicon_init_params_cb(&upd);
timestamp_add_now(TS_FSP_SILICON_INIT_START);
post_code(POST_FSP_SILICON_INIT);
silicon_init = (void *) (hdr->image_base +
hdr->silicon_init_entry_offset);
status = silicon_init(&upd);
timestamp_add_now(TS_FSP_SILICON_INIT_END);
post_code(POST_FSP_SILICON_INIT);
printk(BIOS_DEBUG, "FspSiliconInit returned 0x%08x\n", status);
return status;
}
void run_ramstage(void)
{
struct prog ramstage =
PROG_INIT(ASSET_RAMSTAGE, CONFIG_CBFS_PREFIX "/ramstage");
/* Only x86 systems currently take the same firmware path on resume. */
if (IS_ENABLED(CONFIG_ARCH_X86) && IS_ENABLED(CONFIG_EARLY_CBMEM_INIT))
run_ramstage_from_resume(romstage_handoff_find_or_add(),
&ramstage);
if (prog_locate(&ramstage))
goto fail;
timestamp_add_now(TS_START_COPYRAM);
if (IS_ENABLED(CONFIG_RELOCATABLE_RAMSTAGE)) {
if (load_relocatable_ramstage(&ramstage))
goto fail;
} else if (cbfs_prog_stage_load(&ramstage))
goto fail;
stage_cache_add(STAGE_RAMSTAGE, &ramstage);
timestamp_add_now(TS_END_COPYRAM);
prog_run(&ramstage);
fail:
die("Ramstage was not loaded!\n");
}
void main(void)
{
extern struct mem_timings mem_timings;
int is_resume = (get_wakeup_state() != IS_NOT_WAKEUP);
int power_init_failed;
exynos5420_config_smp();
power_init_failed = setup_power(is_resume);
timestamp_init(timestamp_get());
timestamp_add_now(TS_START_ROMSTAGE);
/* Clock must be initialized before console_init, otherwise you may need
* to re-initialize serial console drivers again. */
system_clock_init();
exynos_pinmux_uart3();
console_init();
exception_init();
if (power_init_failed)
die("Failed to intialize power.\n");
/* re-initialize PMIC I2C channel after (re-)setting system clocks */
i2c_init(PMIC_I2C_BUS, 1000000, 0x00); /* 1MHz */
timestamp_add_now(TS_BEFORE_INITRAM);
setup_memory(&mem_timings, is_resume);
timestamp_add_now(TS_AFTER_INITRAM);
primitive_mem_test();
trustzone_init();
if (is_resume) {
wakeup();
}
setup_gpio();
setup_ec();
simple_spi_test();
/* Set SPI (primary CBFS media) clock to 50MHz. */
/* if this is uncommented SPI will not work correctly. */
clock_set_rate(PERIPH_ID_SPI1, 50000000);
exynos_pinmux_spi1();
simple_spi_test();
cbmem_initialize_empty();
simple_spi_test();
timestamp_add_now(TS_END_ROMSTAGE);
run_ramstage();
}
static void fsp_run_silicon_init(int is_s3_wakeup)
{
FSP_INFO_HEADER *fsp_info_header;
FSP_SILICON_INIT fsp_silicon_init;
SILICON_INIT_UPD *original_params;
SILICON_INIT_UPD silicon_init_params;
EFI_STATUS status;
UPD_DATA_REGION *upd_ptr;
VPD_DATA_REGION *vpd_ptr;
/* Find the FSP image */
fsp_info_header = fsp_get_fih();
if (fsp_info_header == NULL) {
printk(BIOS_ERR, "FSP_INFO_HEADER not set!\n");
return;
}
print_fsp_info(fsp_info_header);
/* Initialize the UPD values */
vpd_ptr = (VPD_DATA_REGION *)(fsp_info_header->CfgRegionOffset +
fsp_info_header->ImageBase);
printk(BIOS_DEBUG, "0x%p: VPD Data\n", vpd_ptr);
upd_ptr = (UPD_DATA_REGION *)(vpd_ptr->PcdUpdRegionOffset +
fsp_info_header->ImageBase);
printk(BIOS_DEBUG, "0x%p: UPD Data\n", upd_ptr);
original_params = (void *)((u8 *)upd_ptr +
upd_ptr->SiliconInitUpdOffset);
memcpy(&silicon_init_params, original_params,
sizeof(silicon_init_params));
soc_silicon_init_params(&silicon_init_params);
/* Locate VBT and pass to FSP GOP */
if (IS_ENABLED(CONFIG_GOP_SUPPORT))
load_vbt(is_s3_wakeup, &silicon_init_params);
mainboard_silicon_init_params(&silicon_init_params);
/* Display the UPD data */
if (IS_ENABLED(CONFIG_DISPLAY_UPD_DATA))
soc_display_silicon_init_params(original_params,
&silicon_init_params);
/* Perform silicon initialization after RAM is configured */
printk(BIOS_DEBUG, "Calling FspSiliconInit\n");
fsp_silicon_init = (FSP_SILICON_INIT)(fsp_info_header->ImageBase
+ fsp_info_header->FspSiliconInitEntryOffset);
timestamp_add_now(TS_FSP_SILICON_INIT_START);
printk(BIOS_DEBUG, "Calling FspSiliconInit(0x%p) at 0x%p\n",
&silicon_init_params, fsp_silicon_init);
status = fsp_silicon_init(&silicon_init_params);
timestamp_add_now(TS_FSP_SILICON_INIT_END);
printk(BIOS_DEBUG, "FspSiliconInit returned 0x%08x\n", status);
display_hob_info(fsp_info_header);
soc_after_silicon_init();
}
size_t cbfs_load_and_decompress(const struct region_device *rdev, size_t offset,
size_t in_size, void *buffer, size_t buffer_size, uint32_t compression)
{
size_t out_size;
switch (compression) {
case CBFS_COMPRESS_NONE:
if (buffer_size < in_size)
return 0;
if (rdev_readat(rdev, buffer, offset, in_size) != in_size)
return 0;
return in_size;
case CBFS_COMPRESS_LZ4:
if ((ENV_BOOTBLOCK || ENV_VERSTAGE) &&
!IS_ENABLED(CONFIG_COMPRESS_PRERAM_STAGES))
return 0;
/* Load the compressed image to the end of the available memory
* area for in-place decompression. It is the responsibility of
* the caller to ensure that buffer_size is large enough
* (see compression.h, guaranteed by cbfstool for stages). */
void *compr_start = buffer + buffer_size - in_size;
if (rdev_readat(rdev, compr_start, offset, in_size) != in_size)
return 0;
timestamp_add_now(TS_START_ULZ4F);
out_size = ulz4fn(compr_start, in_size, buffer, buffer_size);
timestamp_add_now(TS_END_ULZ4F);
return out_size;
case CBFS_COMPRESS_LZMA:
if (ENV_BOOTBLOCK || ENV_VERSTAGE)
return 0;
if ((ENV_ROMSTAGE || ENV_POSTCAR)
&& !IS_ENABLED(CONFIG_COMPRESS_RAMSTAGE))
return 0;
void *map = rdev_mmap(rdev, offset, in_size);
if (map == NULL)
return 0;
/* Note: timestamp not useful for memory-mapped media (x86) */
timestamp_add_now(TS_START_ULZMA);
out_size = ulzman(map, in_size, buffer, buffer_size);
timestamp_add_now(TS_END_ULZMA);
rdev_munmap(rdev, map);
return out_size;
default:
return 0;
}
}
/**
* Extract a node to given regions.
* Returns true on error, false on success.
*/
static bool extract(struct region *region, struct fit_image_node *node)
{
void *dst = (void *)region->offset;
const char *comp_name;
size_t true_size = 0;
switch (node->compression) {
case CBFS_COMPRESS_NONE:
comp_name = "Relocating uncompressed";
break;
case CBFS_COMPRESS_LZMA:
comp_name = "Decompressing LZMA";
break;
case CBFS_COMPRESS_LZ4:
comp_name = "Decompressing LZ4";
break;
default:
printk(BIOS_ERR, "ERROR: Unsupported compression\n");
return true;
}
printk(BIOS_INFO, "FIT: %s %s to %p\n", comp_name, node->name, dst);
switch (node->compression) {
case CBFS_COMPRESS_NONE:
memcpy(dst, node->data, node->size);
true_size = node->size;
break;
case CBFS_COMPRESS_LZMA:
timestamp_add_now(TS_START_ULZMA);
true_size = ulzman(node->data, node->size, dst, region->size);
timestamp_add_now(TS_END_ULZMA);
break;
case CBFS_COMPRESS_LZ4:
timestamp_add_now(TS_START_ULZ4F);
true_size = ulz4fn(node->data, node->size, dst, region->size);
timestamp_add_now(TS_END_ULZ4F);
break;
default:
return true;
}
if (!true_size) {
printk(BIOS_ERR, "ERROR: %s node failed!\n", comp_name);
return true;
}
prog_segment_loaded(region->offset, true_size, 0);
return false;
}
asmlinkage void *romstage_main(FSP_INFO_HEADER *fih)
{
void *top_of_stack;
struct pei_data pei_data;
struct romstage_params params = {
.pei_data = &pei_data,
.chipset_context = fih,
};
post_code(0x30);
timestamp_add_now(TS_START_ROMSTAGE);
/* Load microcode before RAM init */
if (IS_ENABLED(CONFIG_SUPPORT_CPU_UCODE_IN_CBFS))
intel_update_microcode_from_cbfs();
memset(&pei_data, 0, sizeof(pei_data));
/* Display parameters */
printk(BIOS_SPEW, "CONFIG_MMCONF_BASE_ADDRESS: 0x%08x\n",
CONFIG_MMCONF_BASE_ADDRESS);
printk(BIOS_INFO, "Using FSP 1.1\n");
/* Display FSP banner */
print_fsp_info(fih);
/* Stash FSP version. */
params.fsp_version = fsp_version(fih);
/* Get power state */
params.power_state = fill_power_state();
/*
* Read and print board version. Done after SOC romstage
* in case PCH needs to be configured to talk to the EC.
*/
if (IS_ENABLED(CONFIG_BOARD_ID_AUTO))
printk(BIOS_INFO, "MLB: board version %d\n", board_id());
/* Call into mainboard. */
mainboard_romstage_entry(¶ms);
soc_after_ram_init(¶ms);
post_code(0x38);
top_of_stack = setup_stack_and_mtrrs();
printk(BIOS_DEBUG, "Calling FspTempRamExit API\n");
timestamp_add_now(TS_FSP_TEMP_RAM_EXIT_START);
return top_of_stack;
}
static void
load_ramstage(const struct prog_loader_ops *ops,
struct romstage_handoff *handoff, struct prog *ramstage)
{
timestamp_add_now(TS_START_COPYRAM);
if (ops->prepare(ramstage))
return;
cache_loaded_ramstage(handoff, ramstage);
timestamp_add_now(TS_END_COPYRAM);
prog_run(ramstage);
}
static void acpi_jump_to_wakeup(void *vector)
{
uintptr_t source = 0, target = 0;
size_t size = 0;
if (!acpi_s3_resume_allowed()) {
printk(BIOS_WARNING, "ACPI: S3 resume not allowed.\n");
return;
}
if (!CONFIG(RELOCATABLE_RAMSTAGE)) {
struct resume_backup *backup_mem = cbmem_find(CBMEM_ID_RESUME);
if (backup_mem && backup_mem->valid) {
backup_mem->valid = 0;
target = backup_mem->lowmem;
source = backup_mem->cbmem;
size = backup_mem->size;
} else {
printk(BIOS_WARNING, "ACPI: Backup memory missing. "
"No S3 resume.\n");
return;
}
}
/* Copy wakeup trampoline in place. */
memcpy((void *)WAKEUP_BASE, &__wakeup, __wakeup_size);
set_boot_successful();
timestamp_add_now(TS_ACPI_WAKE_JUMP);
acpi_do_wakeup((uintptr_t)vector, source, target, size);
}
void perform_raminit(int s3resume)
{
int cbmem_was_initted;
struct pei_data pei_data;
/* Prepare USB controller early in S3 resume */
if (!mainboard_should_reset_usb(s3resume))
enable_usb_bar();
mainboard_fill_pei_data(&pei_data);
post_code(0x3a);
pei_data.boot_mode = s3resume ? 2 : 0;
timestamp_add_now(TS_BEFORE_INITRAM);
sdram_initialize(&pei_data);
cbmem_was_initted = !cbmem_recovery(s3resume);
if (!s3resume)
save_mrc_data(&pei_data);
if (s3resume && !cbmem_was_initted) {
/* Failed S3 resume, reset to come up cleanly */
outb(0x6, 0xcf9);
halt();
}
}
void acpi_jump_to_wakeup(void *vector)
{
u32 acpi_backup_memory = 0;
if (HIGH_MEMORY_SAVE && acpi_s3_resume_allowed()) {
acpi_backup_memory = (u32)cbmem_find(CBMEM_ID_RESUME);
if (!acpi_backup_memory) {
printk(BIOS_WARNING, "ACPI: Backup memory missing. "
"No S3 resume.\n");
return;
}
}
#if CONFIG_SMP
// FIXME: This should go into the ACPI backup memory, too. No pork sausages.
/*
* Just restore the SMP trampoline and continue with wakeup on
* assembly level.
*/
memcpy(lowmem_backup_ptr, lowmem_backup, lowmem_backup_size);
#endif
/* Copy wakeup trampoline in place. */
memcpy((void *)WAKEUP_BASE, &__wakeup, __wakeup_size);
#if CONFIG_COLLECT_TIMESTAMPS
timestamp_add_now(TS_ACPI_WAKE_JUMP);
#endif
acpi_do_wakeup((u32)vector, acpi_backup_memory, CONFIG_RAMBASE,
HIGH_MEMORY_SAVE);
}
void romstage_init(void)
{
void *entry;
#if CONFIG_COLLECT_TIMESTAMPS
uint64_t start_romstage_time;
uint64_t before_dram_time;
uint64_t after_dram_time;
uint64_t base_time = timestamp_get();
start_romstage_time = timestamp_get();
#endif
rkclk_set_pll();
console_init();
#if CONFIG_COLLECT_TIMESTAMPS
before_dram_time = timestamp_get();
#endif
dram_main();
#if CONFIG_COLLECT_TIMESTAMPS
after_dram_time = timestamp_get();
#endif
udelay(100);
cbmem_initialize_empty();
#if CONFIG_COLLECT_TIMESTAMPS
timestamp_init(base_time);
timestamp_add(TS_START_ROMSTAGE, start_romstage_time );
timestamp_add(TS_BEFORE_INITRAM, before_dram_time );
timestamp_add(TS_AFTER_INITRAM, after_dram_time );
#endif
entry = cbfs_load_stage(CBFS_DEFAULT_MEDIA, "fallback/coreboot_ram");
#if CONFIG_COLLECT_TIMESTAMPS
timestamp_add_now(TS_END_ROMSTAGE);
#endif
stage_exit(entry);
}
VbError_t VbExDiskGetInfo(VbDiskInfo **info_ptr, uint32_t *count,
uint32_t disk_flags)
{
*count = 0;
blockdev_type_t bd_type;
ListNode *devs;
if (disk_flags & VB_DISK_FLAG_FIXED)
bd_type = BLOCKDEV_FIXED;
else
bd_type = BLOCKDEV_REMOVABLE;
*count = get_all_bdevs(bd_type, &devs);
// Only log for fixed disks to avoid spamming timestamps in recovery.
if (disk_flags & VB_DISK_FLAG_FIXED)
timestamp_add_now(TS_VB_STORAGE_INIT_DONE);
// Allocate enough VbDiskInfo structures.
VbDiskInfo *disk = NULL;
if (*count)
disk = xzalloc(sizeof(VbDiskInfo) * *count);
*info_ptr = disk;
// Fill them from the BlockDev structures.
BlockDev *bdev;
list_for_each(bdev, *devs, list_node)
setup_vb_disk_info(disk++, bdev);
return VBERROR_SUCCESS;
}
asmlinkage void after_cache_as_ram(void *chipset_context)
{
timestamp_add_now(TS_FSP_TEMP_RAM_EXIT_END);
printk(BIOS_DEBUG, "FspTempRamExit returned successfully\n");
soc_display_mtrrs();
after_cache_as_ram_stage();
}
void asmlinkage romstage_after_car(void)
{
timestamp_add_now(TS_END_ROMSTAGE);
/* Load the ramstage. */
copy_and_run();
while (1);
}
void romstage(void)
{
timestamp_add_now(TS_START_ROMSTAGE);
console_init();
exception_init();
printk(BIOS_INFO, "T132: romstage here\n");
#if CONFIG_BOOTROM_SDRAM_INIT
printk(BIOS_INFO, "T132 romstage: SDRAM init done by BootROM, RAMCODE = %d\n",
sdram_get_ram_code());
#else
sdram_init(get_sdram_config());
printk(BIOS_INFO, "T132 romstage: sdram_init done\n");
#endif
timestamp_add_now(TS_AFTER_INITRAM);
/*
* Trust Zone needs to be initialized after the DRAM initialization
* because carveout registers are programmed during DRAM init.
* cbmem_initialize() is dependent on the Trust Zone region
* initalization because CBMEM lives right below the Trust Zone which
* needs to be properly identified.
*/
trustzone_region_init();
/*
* When romstage is running it's always on the reboot path -- never a
* resume path where cbmem recovery is required. Therefore, always
* initialize the cbmem area to be empty.
*/
cbmem_initialize_empty();
ccplex_cpu_prepare();
printk(BIOS_INFO, "T132 romstage: cpu prepare done\n");
ccplex_load_mts();
printk(BIOS_INFO, "T132 romstage: MTS loading done\n");
romstage_mainboard_init();
run_ramstage();
}
static boot_state_t bs_dev_resources(void *arg)
{
timestamp_add_now(TS_DEVICE_CONFIGURE);
/* Now compute and assign the bus resources. */
dev_configure();
return BS_DEV_ENABLE;
}
static boot_state_t bs_dev_enable(void *arg)
{
timestamp_add_now(TS_DEVICE_ENABLE);
/* Now actually enable devices on the bus */
dev_enable();
return BS_DEV_INIT;
}
static boot_state_t bs_dev_init(void *arg)
{
timestamp_add_now(TS_DEVICE_INITIALIZE);
/* And of course initialize devices on the bus */
dev_initialize();
return BS_POST_DEVICE;
}
static boot_state_t bs_dev_init_chips(void *arg)
{
timestamp_add_now(TS_DEVICE_ENUMERATE);
/* Initialize chips early, they might disable unused devices. */
dev_initialize_chips();
return BS_DEV_ENUMERATE;
}
static boot_state_t bs_post_device(void *arg)
{
dev_finalize();
timestamp_add_now(TS_DEVICE_DONE);
timestamp_reinit();
return BS_OS_RESUME_CHECK;
}
asmlinkage void car_stage_entry(void)
{
console_init();
cbmem_recovery(0);
timestamp_add_now(TS_START_ROMSTAGE);
run_ramstage();
}
void main(void)
{
struct mem_timings *mem;
int is_resume = (get_wakeup_state() != IS_NOT_WAKEUP);
timestamp_init(timestamp_get());
timestamp_add_now(TS_START_ROMSTAGE);
/* Clock must be initialized before console_init, otherwise you may need
* to re-initialize serial console drivers again. */
mem = setup_clock();
console_init();
exception_init();
setup_power(is_resume);
timestamp_add_now(TS_BEFORE_INITRAM);
setup_memory(mem, is_resume);
timestamp_add_now(TS_AFTER_INITRAM);
/* This needs to happen on normal boots and on resume. */
trustzone_init();
if (is_resume) {
wakeup();
}
setup_gpio();
setup_graphics();
/* Set SPI (primary CBFS media) clock to 50MHz and configure pinmux. */
exynos_pinmux_spi1();
clock_set_rate(PERIPH_ID_SPI1, 50000000);
cbmem_initialize_empty();
timestamp_add_now(TS_END_ROMSTAGE);
run_ramstage();
}
/*******************************************************************************
* The FSP early_init function returns to this function.
* Memory is setup and the stack is set by the FSP.
*/
void romstage_main_continue(EFI_STATUS status, void *hob_list_ptr) {
int cbmem_was_initted;
void *cbmem_hob_ptr;
uint32_t prev_sleep_state;
struct romstage_handoff *handoff;
timestamp_add_now(TS_AFTER_INITRAM);
post_code(0x4a);
printk(BIOS_DEBUG, "%s status: %x hob_list_ptr: %x\n",
__func__, (u32) status, (u32) hob_list_ptr);
#if IS_ENABLED(CONFIG_USBDEBUG_IN_ROMSTAGE)
/* FSP reconfigures USB, so reinit it to have debug */
usbdebug_init();
#endif /* IS_ENABLED(CONFIG_USBDEBUG_IN_ROMSTAGE) */
printk(BIOS_DEBUG, "FSP Status: 0x%0x\n", (u32)status);
/* Get previous sleep state again and clear */
prev_sleep_state = chipset_prev_sleep_state(1);
printk(BIOS_DEBUG, "%s: prev_sleep_state = S%d\n", __func__, prev_sleep_state);
report_platform_info();
post_code(0x4b);
late_mainboard_romstage_entry();
post_code(0x4c);
/* if S3 resume skip ram check */
if (prev_sleep_state != 3) {
quick_ram_check();
post_code(0x4d);
}
cbmem_was_initted = !cbmem_recovery(prev_sleep_state == 3);
/* Save the HOB pointer in CBMEM to be used in ramstage*/
cbmem_hob_ptr = cbmem_add (CBMEM_ID_HOB_POINTER, sizeof(*hob_list_ptr));
*(u32*)cbmem_hob_ptr = (u32)hob_list_ptr;
post_code(0x4e);
handoff = romstage_handoff_find_or_add();
if (handoff != NULL)
handoff->s3_resume = (prev_sleep_state == 3);
else
printk(BIOS_DEBUG, "Romstage handoff structure not added!\n");
post_code(0x4f);
/* Load the ramstage. */
copy_and_run();
while (1);
}
