static void set_sdc_power_ctrl()
{
/* Drive strength configs for sdc pins */
struct tlmm_cfgs sdc1_hdrv_cfg[] =
{
{ SDC1_CLK_HDRV_CTL_OFF, TLMM_CUR_VAL_16MA, TLMM_HDRV_MASK, 0},
{ SDC1_CMD_HDRV_CTL_OFF, TLMM_CUR_VAL_10MA, TLMM_HDRV_MASK, 0},
{ SDC1_DATA_HDRV_CTL_OFF, TLMM_CUR_VAL_10MA, TLMM_HDRV_MASK , 0},
};
/* Pull configs for sdc pins */
struct tlmm_cfgs sdc1_pull_cfg[] =
{
{ SDC1_CLK_PULL_CTL_OFF, TLMM_NO_PULL, TLMM_PULL_MASK, 0},
{ SDC1_CMD_PULL_CTL_OFF, TLMM_PULL_UP, TLMM_PULL_MASK, 0},
{ SDC1_DATA_PULL_CTL_OFF, TLMM_PULL_UP, TLMM_PULL_MASK, 0},
};
struct tlmm_cfgs sdc1_rclk_cfg[] =
{
{ SDC1_RCLK_PULL_CTL_OFF, TLMM_PULL_DOWN, TLMM_PULL_MASK, 0},
};
/* Set the drive strength & pull control values */
tlmm_set_hdrive_ctrl(sdc1_hdrv_cfg, ARRAY_SIZE(sdc1_hdrv_cfg));
tlmm_set_pull_ctrl(sdc1_pull_cfg, ARRAY_SIZE(sdc1_pull_cfg));
tlmm_set_pull_ctrl(sdc1_rclk_cfg, ARRAY_SIZE(sdc1_rclk_cfg));
}
static void set_sdc_power_ctrl()
{
uint8_t tlmm_hdrv_clk = 0;
uint32_t platform_id = 0;
platform_id = board_platform_id();
switch(platform_id)
{
case MSM8274AA:
case MSM8274AB:
case MSM8674AA:
case MSM8674AB:
case MSM8974AA:
case MSM8974AB:
if (board_hardware_id() == HW_PLATFORM_MTP)
tlmm_hdrv_clk = TLMM_CUR_VAL_10MA;
else
tlmm_hdrv_clk = TLMM_CUR_VAL_16MA;
break;
default:
tlmm_hdrv_clk = TLMM_CUR_VAL_16MA;
};
/* Drive strength configs for sdc pins */
struct tlmm_cfgs sdc1_hdrv_cfg[] =
{
{ SDC1_CLK_HDRV_CTL_OFF, tlmm_hdrv_clk, TLMM_HDRV_MASK },
{ SDC1_CMD_HDRV_CTL_OFF, TLMM_CUR_VAL_10MA, TLMM_HDRV_MASK },
{ SDC1_DATA_HDRV_CTL_OFF, TLMM_CUR_VAL_10MA, TLMM_HDRV_MASK },
};
/* Pull configs for sdc pins */
struct tlmm_cfgs sdc1_pull_cfg[] =
{
{ SDC1_CLK_PULL_CTL_OFF, TLMM_NO_PULL, TLMM_PULL_MASK },
{ SDC1_CMD_PULL_CTL_OFF, TLMM_PULL_UP, TLMM_PULL_MASK },
{ SDC1_DATA_PULL_CTL_OFF, TLMM_PULL_UP, TLMM_PULL_MASK },
};
struct tlmm_cfgs sdc1_rclk_cfg[] =
{
{ SDC1_RCLK_PULL_CTL_OFF, TLMM_PULL_DOWN, TLMM_PULL_MASK },
};
/* Set the drive strength & pull control values */
tlmm_set_hdrive_ctrl(sdc1_hdrv_cfg, ARRAY_SIZE(sdc1_hdrv_cfg));
tlmm_set_pull_ctrl(sdc1_pull_cfg, ARRAY_SIZE(sdc1_pull_cfg));
/* RCLK is supported only with 8974 pro, set rclk to pull down
* only for 8974 pro targets
*/
if (!platform_is_8974())
tlmm_set_pull_ctrl(sdc1_rclk_cfg, ARRAY_SIZE(sdc1_rclk_cfg));
}
static void set_sdc_power_ctrl(uint8_t slot)
{
uint32_t reg = 0;
uint8_t clk;
uint8_t cmd;
uint8_t dat;
if (slot == 0x1)
{
clk = TLMM_CUR_VAL_10MA;
cmd = TLMM_CUR_VAL_8MA;
dat = TLMM_CUR_VAL_8MA;
reg = SDC1_HDRV_PULL_CTL;
}
else if (slot == 0x2)
{
clk = TLMM_CUR_VAL_16MA;
cmd = TLMM_CUR_VAL_10MA;
dat = TLMM_CUR_VAL_10MA;
reg = SDC2_HDRV_PULL_CTL;
}
else
{
dprintf(CRITICAL, "Unsupported SDC slot passed\n");
return;
}
/* Drive strength configs for sdc pins */
struct tlmm_cfgs sdc1_hdrv_cfg[] =
{
{ SDC1_CLK_HDRV_CTL_OFF, clk, TLMM_HDRV_MASK, reg },
{ SDC1_CMD_HDRV_CTL_OFF, cmd, TLMM_HDRV_MASK, reg },
{ SDC1_DATA_HDRV_CTL_OFF, dat, TLMM_HDRV_MASK, reg },
};
/* Pull configs for sdc pins */
struct tlmm_cfgs sdc1_pull_cfg[] =
{
{ SDC1_CLK_PULL_CTL_OFF, TLMM_NO_PULL, TLMM_PULL_MASK, reg },
{ SDC1_CMD_PULL_CTL_OFF, TLMM_PULL_UP, TLMM_PULL_MASK, reg },
{ SDC1_DATA_PULL_CTL_OFF, TLMM_PULL_UP, TLMM_PULL_MASK, reg },
};
struct tlmm_cfgs sdc1_rclk_cfg[] =
{
{ SDC1_RCLK_PULL_CTL_OFF, TLMM_PULL_DOWN, TLMM_PULL_MASK, reg },
};
/* Set the drive strength & pull control values */
tlmm_set_hdrive_ctrl(sdc1_hdrv_cfg, ARRAY_SIZE(sdc1_hdrv_cfg));
tlmm_set_pull_ctrl(sdc1_pull_cfg, ARRAY_SIZE(sdc1_pull_cfg));
tlmm_set_pull_ctrl(sdc1_rclk_cfg, ARRAY_SIZE(sdc1_rclk_cfg));
}
static void set_sdc_power_ctrl(uint8_t slot)
{
uint32_t reg = 0;
if (slot == 0x1)
reg = SDC1_HDRV_PULL_CTL;
else if (slot == 0x2)
reg = SDC2_HDRV_PULL_CTL;
/* Drive strength configs for sdc pins */
struct tlmm_cfgs sdc1_hdrv_cfg[] =
{
{ SDC1_CLK_HDRV_CTL_OFF, TLMM_CUR_VAL_16MA, TLMM_HDRV_MASK, reg },
{ SDC1_CMD_HDRV_CTL_OFF, TLMM_CUR_VAL_10MA, TLMM_HDRV_MASK, reg },
{ SDC1_DATA_HDRV_CTL_OFF, TLMM_CUR_VAL_6MA, TLMM_HDRV_MASK, reg },
};
/* Pull configs for sdc pins */
struct tlmm_cfgs sdc1_pull_cfg[] =
{
{ SDC1_CLK_PULL_CTL_OFF, TLMM_NO_PULL, TLMM_PULL_MASK, reg },
{ SDC1_CMD_PULL_CTL_OFF, TLMM_PULL_UP, TLMM_PULL_MASK, reg },
{ SDC1_DATA_PULL_CTL_OFF, TLMM_PULL_UP, TLMM_PULL_MASK, reg },
};
/* Set the drive strength & pull control values */
tlmm_set_hdrive_ctrl(sdc1_hdrv_cfg, ARRAY_SIZE(sdc1_hdrv_cfg));
tlmm_set_pull_ctrl(sdc1_pull_cfg, ARRAY_SIZE(sdc1_pull_cfg));
}
