static void create_bcc_state( struct brw_depth_stencil_state *zstencil,
const struct pipe_depth_stencil_alpha_state *templ )
{
if (templ->stencil[0].enabled) {
zstencil->cc0.stencil_enable = 1;
zstencil->cc0.stencil_func =
brw_translate_compare_func(templ->stencil[0].func);
zstencil->cc0.stencil_fail_op =
translate_stencil_op(templ->stencil[0].fail_op);
zstencil->cc0.stencil_pass_depth_fail_op =
translate_stencil_op(templ->stencil[0].zfail_op);
zstencil->cc0.stencil_pass_depth_pass_op =
translate_stencil_op(templ->stencil[0].zpass_op);
zstencil->cc1.stencil_write_mask = templ->stencil[0].writemask;
zstencil->cc1.stencil_test_mask = templ->stencil[0].valuemask;
if (templ->stencil[1].enabled) {
zstencil->cc0.bf_stencil_enable = 1;
zstencil->cc0.bf_stencil_func =
brw_translate_compare_func(templ->stencil[1].func);
zstencil->cc0.bf_stencil_fail_op =
translate_stencil_op(templ->stencil[1].fail_op);
zstencil->cc0.bf_stencil_pass_depth_fail_op =
translate_stencil_op(templ->stencil[1].zfail_op);
zstencil->cc0.bf_stencil_pass_depth_pass_op =
translate_stencil_op(templ->stencil[1].zpass_op);
zstencil->cc2.bf_stencil_write_mask = templ->stencil[1].writemask;
zstencil->cc2.bf_stencil_test_mask = templ->stencil[1].valuemask;
}
zstencil->cc0.stencil_write_enable = (zstencil->cc1.stencil_write_mask ||
zstencil->cc2.bf_stencil_write_mask);
}
if (templ->alpha.enabled) {
zstencil->cc3.alpha_test = 1;
zstencil->cc3.alpha_test_func = brw_translate_compare_func(templ->alpha.func);
zstencil->cc3.alpha_test_format = BRW_ALPHATEST_FORMAT_UNORM8;
zstencil->cc7.alpha_ref.ub[0] = float_to_ubyte(templ->alpha.ref_value);
}
if (templ->depth.enabled) {
zstencil->cc2.depth_test = 1;
zstencil->cc2.depth_test_function = brw_translate_compare_func(templ->depth.func);
zstencil->cc2.depth_write_enable = templ->depth.writemask;
}
}
static void *etna_pipe_create_depth_stencil_alpha_state(struct pipe_context *pipe,
const struct pipe_depth_stencil_alpha_state *dsa_p)
{
//struct etna_pipe_context *priv = etna_pipe_context(pipe);
struct compiled_depth_stencil_alpha_state *cs = CALLOC_STRUCT(compiled_depth_stencil_alpha_state);
struct pipe_depth_stencil_alpha_state dsa = *dsa_p;
/* XXX does stencil[0] / stencil[1] order depend on rs->front_ccw? */
bool early_z = true;
bool disable_zs = !dsa.depth.writemask;
int i;
/* Set operations to KEEP if write mask is 0.
* When we don't do this, the depth buffer is written for the entire primitive instead of
* just where the stencil condition holds (GC600 rev 0x0019, without feature CORRECT_STENCIL).
* Not sure if this is a hardware bug or just a strange edge case.
*/
for(i=0; i<2; ++i)
{
if(dsa.stencil[i].writemask == 0)
{
dsa.stencil[i].fail_op = dsa.stencil[i].zfail_op = dsa.stencil[i].zpass_op = PIPE_STENCIL_OP_KEEP;
}
}
/* Determine whether to enable early z reject. Don't enable it when any of
* the stencil-modifying functions is used. */
if(dsa.stencil[0].enabled)
{
if(dsa.stencil[0].fail_op != PIPE_STENCIL_OP_KEEP ||
dsa.stencil[0].zfail_op != PIPE_STENCIL_OP_KEEP ||
dsa.stencil[0].zpass_op != PIPE_STENCIL_OP_KEEP)
{
disable_zs = early_z = false;
}
else if(dsa.stencil[1].enabled)
{
if(dsa.stencil[1].fail_op != PIPE_STENCIL_OP_KEEP ||
dsa.stencil[1].zfail_op != PIPE_STENCIL_OP_KEEP ||
dsa.stencil[1].zpass_op != PIPE_STENCIL_OP_KEEP)
{
disable_zs = early_z = false;
}
}
}
/* compare funcs have 1 to 1 mapping */
cs->PE_DEPTH_CONFIG =
VIVS_PE_DEPTH_CONFIG_DEPTH_FUNC(dsa.depth.enabled ? dsa.depth.func : PIPE_FUNC_ALWAYS) |
(dsa.depth.writemask ? VIVS_PE_DEPTH_CONFIG_WRITE_ENABLE : 0) |
(early_z ? VIVS_PE_DEPTH_CONFIG_EARLY_Z : 0) |
(disable_zs ? VIVS_PE_DEPTH_CONFIG_DISABLE_ZS : 0);
cs->PE_ALPHA_OP =
(dsa.alpha.enabled ? VIVS_PE_ALPHA_OP_ALPHA_TEST : 0) |
VIVS_PE_ALPHA_OP_ALPHA_FUNC(dsa.alpha.func) |
VIVS_PE_ALPHA_OP_ALPHA_REF(etna_cfloat_to_uint8(dsa.alpha.ref_value));
cs->PE_STENCIL_OP =
VIVS_PE_STENCIL_OP_FUNC_FRONT(dsa.stencil[0].func) |
VIVS_PE_STENCIL_OP_FUNC_BACK(dsa.stencil[1].func) |
VIVS_PE_STENCIL_OP_FAIL_FRONT(translate_stencil_op(dsa.stencil[0].fail_op)) |
VIVS_PE_STENCIL_OP_FAIL_BACK(translate_stencil_op(dsa.stencil[1].fail_op)) |
VIVS_PE_STENCIL_OP_DEPTH_FAIL_FRONT(translate_stencil_op(dsa.stencil[0].zfail_op)) |
VIVS_PE_STENCIL_OP_DEPTH_FAIL_BACK(translate_stencil_op(dsa.stencil[1].zfail_op)) |
VIVS_PE_STENCIL_OP_PASS_FRONT(translate_stencil_op(dsa.stencil[0].zpass_op)) |
VIVS_PE_STENCIL_OP_PASS_BACK(translate_stencil_op(dsa.stencil[1].zpass_op));
cs->PE_STENCIL_CONFIG =
translate_stencil_mode(dsa.stencil[0].enabled, dsa.stencil[1].enabled) |
VIVS_PE_STENCIL_CONFIG_MASK_FRONT(dsa.stencil[0].valuemask) |
VIVS_PE_STENCIL_CONFIG_WRITE_MASK(dsa.stencil[0].writemask);
/* XXX back masks in VIVS_PE_DEPTH_CONFIG_EXT? */
/* XXX VIVS_PE_STENCIL_CONFIG_REF_FRONT comes from pipe_stencil_ref */
/* XXX does alpha/stencil test affect PE_COLOR_FORMAT_OVERWRITE? */
return cs;
}
