static inline void bswap_fstore(struct fstore *f) { tswap32s(&f->fst_flags); tswap32s(&f->fst_posmode); tswap64s(&f->fst_offset); tswap64s(&f->fst_length); tswap64s(&f->fst_bytesalloc); }
static inline void bswap_flock(struct flock *f) { tswap64s(&f->l_start); tswap64s(&f->l_len); tswap32s(&f->l_pid); tswap16s(&f->l_type); tswap16s(&f->l_whence); }
static inline void byteswap_stat(struct stat *s) { tswap32s((uint32_t*)&s->st_dev); tswap32s(&s->st_ino); tswap16s(&s->st_mode); tswap16s(&s->st_nlink); tswap32s(&s->st_uid); tswap32s(&s->st_gid); tswap32s((uint32_t*)&s->st_rdev); tswap32s((uint32_t*)&s->st_atimespec.tv_sec); tswap32s((uint32_t*)&s->st_atimespec.tv_nsec); tswap32s((uint32_t*)&s->st_mtimespec.tv_sec); tswap32s((uint32_t*)&s->st_mtimespec.tv_nsec); tswap32s((uint32_t*)&s->st_ctimespec.tv_sec); tswap32s((uint32_t*)&s->st_ctimespec.tv_nsec); tswap64s((uint64_t*)&s->st_size); tswap64s((uint64_t*)&s->st_blocks); tswap32s((uint32_t*)&s->st_blksize); tswap32s(&s->st_flags); tswap32s(&s->st_gen); }
static void qtest_process_command(CharDriverState *chr, gchar **words) { const gchar *command; g_assert(words); command = words[0]; if (qtest_log_fp) { qemu_timeval tv; int i; qtest_get_time(&tv); fprintf(qtest_log_fp, "[R +" FMT_timeval "]", (long) tv.tv_sec, (long) tv.tv_usec); for (i = 0; words[i]; i++) { fprintf(qtest_log_fp, " %s", words[i]); } fprintf(qtest_log_fp, "\n"); } g_assert(command); if (strcmp(words[0], "irq_intercept_out") == 0 || strcmp(words[0], "irq_intercept_in") == 0) { DeviceState *dev; g_assert(words[1]); dev = DEVICE(object_resolve_path(words[1], NULL)); if (!dev) { qtest_send_prefix(chr); qtest_send(chr, "FAIL Unknown device\n"); return; } if (irq_intercept_dev) { qtest_send_prefix(chr); if (irq_intercept_dev != dev) { qtest_send(chr, "FAIL IRQ intercept already enabled\n"); } else { qtest_send(chr, "OK\n"); } return; } if (words[0][14] == 'o') { qemu_irq_intercept_out(&dev->gpio_out, qtest_irq_handler, dev->num_gpio_out); } else { qemu_irq_intercept_in(dev->gpio_in, qtest_irq_handler, dev->num_gpio_in); } irq_intercept_dev = dev; qtest_send_prefix(chr); qtest_send(chr, "OK\n"); } else if (strcmp(words[0], "outb") == 0 || strcmp(words[0], "outw") == 0 || strcmp(words[0], "outl") == 0) { uint16_t addr; uint32_t value; g_assert(words[1] && words[2]); addr = strtoul(words[1], NULL, 0); value = strtoul(words[2], NULL, 0); if (words[0][3] == 'b') { cpu_outb(addr, value); } else if (words[0][3] == 'w') { cpu_outw(addr, value); } else if (words[0][3] == 'l') { cpu_outl(addr, value); } qtest_send_prefix(chr); qtest_send(chr, "OK\n"); } else if (strcmp(words[0], "inb") == 0 || strcmp(words[0], "inw") == 0 || strcmp(words[0], "inl") == 0) { uint16_t addr; uint32_t value = -1U; g_assert(words[1]); addr = strtoul(words[1], NULL, 0); if (words[0][2] == 'b') { value = cpu_inb(addr); } else if (words[0][2] == 'w') { value = cpu_inw(addr); } else if (words[0][2] == 'l') { value = cpu_inl(addr); } qtest_send_prefix(chr); qtest_send(chr, "OK 0x%04x\n", value); } else if (strcmp(words[0], "writeb") == 0 || strcmp(words[0], "writew") == 0 || strcmp(words[0], "writel") == 0 || strcmp(words[0], "writeq") == 0) { uint64_t addr; uint64_t value; g_assert(words[1] && words[2]); addr = strtoull(words[1], NULL, 0); value = strtoull(words[2], NULL, 0); if (words[0][5] == 'b') { uint8_t data = value; cpu_physical_memory_write(addr, &data, 1); } else if (words[0][5] == 'w') { uint16_t data = value; tswap16s(&data); cpu_physical_memory_write(addr, &data, 2); } else if (words[0][5] == 'l') { uint32_t data = value; tswap32s(&data); cpu_physical_memory_write(addr, &data, 4); } else if (words[0][5] == 'q') { uint64_t data = value; tswap64s(&data); cpu_physical_memory_write(addr, &data, 8); } qtest_send_prefix(chr); qtest_send(chr, "OK\n"); } else if (strcmp(words[0], "readb") == 0 || strcmp(words[0], "readw") == 0 || strcmp(words[0], "readl") == 0 || strcmp(words[0], "readq") == 0) { uint64_t addr; uint64_t value = UINT64_C(-1); g_assert(words[1]); addr = strtoull(words[1], NULL, 0); if (words[0][4] == 'b') { uint8_t data; cpu_physical_memory_read(addr, &data, 1); value = data; } else if (words[0][4] == 'w') { uint16_t data; cpu_physical_memory_read(addr, &data, 2); value = tswap16(data); } else if (words[0][4] == 'l') { uint32_t data; cpu_physical_memory_read(addr, &data, 4); value = tswap32(data); } else if (words[0][4] == 'q') { cpu_physical_memory_read(addr, &value, 8); tswap64s(&value); } qtest_send_prefix(chr); qtest_send(chr, "OK 0x%016" PRIx64 "\n", value); } else if (strcmp(words[0], "read") == 0) { uint64_t addr, len, i; uint8_t *data; g_assert(words[1] && words[2]); addr = strtoull(words[1], NULL, 0); len = strtoull(words[2], NULL, 0); data = g_malloc(len); cpu_physical_memory_read(addr, data, len); qtest_send_prefix(chr); qtest_send(chr, "OK 0x"); for (i = 0; i < len; i++) { qtest_send(chr, "%02x", data[i]); } qtest_send(chr, "\n"); g_free(data); } else if (strcmp(words[0], "write") == 0) { uint64_t addr, len, i; uint8_t *data; size_t data_len; g_assert(words[1] && words[2] && words[3]); addr = strtoull(words[1], NULL, 0); len = strtoull(words[2], NULL, 0); data_len = strlen(words[3]); if (data_len < 3) { qtest_send(chr, "ERR invalid argument size\n"); return; } data = g_malloc(len); for (i = 0; i < len; i++) { if ((i * 2 + 4) <= data_len) { data[i] = hex2nib(words[3][i * 2 + 2]) << 4; data[i] |= hex2nib(words[3][i * 2 + 3]); } else { data[i] = 0; } } cpu_physical_memory_write(addr, data, len); g_free(data); qtest_send_prefix(chr); qtest_send(chr, "OK\n"); } else if (qtest_enabled() && strcmp(words[0], "clock_step") == 0) { int64_t ns; if (words[1]) { ns = strtoll(words[1], NULL, 0); } else { ns = qemu_clock_deadline_ns_all(QEMU_CLOCK_VIRTUAL); } qtest_clock_warp(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + ns); qtest_send_prefix(chr); qtest_send(chr, "OK %"PRIi64"\n", (int64_t)qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL)); } else if (qtest_enabled() && strcmp(words[0], "clock_set") == 0) { int64_t ns; g_assert(words[1]); ns = strtoll(words[1], NULL, 0); qtest_clock_warp(ns); qtest_send_prefix(chr); qtest_send(chr, "OK %"PRIi64"\n", (int64_t)qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL)); } else { qtest_send_prefix(chr); qtest_send(chr, "FAIL Unknown command `%s'\n", words[0]); } }
long do_mach_syscall(void *cpu_env, int num, uint32_t arg1, uint32_t arg2, uint32_t arg3, uint32_t arg4, uint32_t arg5, uint32_t arg6, uint32_t arg7, uint32_t arg8) { extern uint32_t mach_reply_port(); long ret = 0; arg1 = tswap32(arg1); arg2 = tswap32(arg2); arg3 = tswap32(arg3); arg4 = tswap32(arg4); arg5 = tswap32(arg5); arg6 = tswap32(arg6); arg7 = tswap32(arg7); arg8 = tswap32(arg8); DPRINTF("mach syscall %d : " , num); switch(num) { /* see xnu/osfmk/mach/syscall_sw.h */ case -26: DPRINTF("mach_reply_port()\n"); ret = mach_reply_port(); break; case -27: DPRINTF("mach_thread_self()\n"); ret = mach_thread_self(); break; case -28: DPRINTF("mach_task_self()\n"); ret = mach_task_self(); break; case -29: DPRINTF("mach_host_self()\n"); ret = mach_host_self(); break; case -31: DPRINTF("mach_msg_trap(0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x)\n", arg1, arg2, arg3, arg4, arg5, arg6, arg7); ret = target_mach_msg_trap((mach_msg_header_t *)arg1, arg2, arg3, arg4, arg5, arg6, arg7); break; /* may need more translation if target arch is different from host */ #if (defined(TARGET_I386) && defined(__i386__)) || (defined(TARGET_PPC) && defined(__ppc__)) case -33: DPRINTF("semaphore_signal_trap(0x%x)\n", arg1); ret = semaphore_signal_trap(arg1); break; case -34: DPRINTF("semaphore_signal_all_trap(0x%x)\n", arg1); ret = semaphore_signal_all_trap(arg1); break; case -35: DPRINTF("semaphore_signal_thread_trap(0x%x)\n", arg1, arg2); ret = semaphore_signal_thread_trap(arg1,arg2); break; #endif case -36: DPRINTF("semaphore_wait_trap(0x%x)\n", arg1); extern int semaphore_wait_trap(int); // XXX: is there any header for that? ret = semaphore_wait_trap(arg1); break; /* may need more translation if target arch is different from host */ #if (defined(TARGET_I386) && defined(__i386__)) || (defined(TARGET_PPC) && defined(__ppc__)) case -37: DPRINTF("semaphore_wait_signal_trap(0x%x, 0x%x)\n", arg1, arg2); ret = semaphore_wait_signal_trap(arg1,arg2); break; #endif case -43: DPRINTF("map_fd(0x%x, 0x%x, 0x%x, 0x%x, 0x%x)\n", arg1, arg2, arg3, arg4, arg5); ret = map_fd(arg1, arg2, (void*)arg3, arg4, arg5); tswap32s((uint32_t*)arg3); break; /* may need more translation if target arch is different from host */ #if (defined(TARGET_I386) && defined(__i386__)) || (defined(TARGET_PPC) && defined(__ppc__)) case -61: DPRINTF("syscall_thread_switch(0x%x, 0x%x, 0x%x)\n", arg1, arg2, arg3); ret = syscall_thread_switch(arg1, arg2, arg3); // just a hint to the scheduler; can drop? break; #endif case -89: DPRINTF("mach_timebase_info(0x%x)\n", arg1); struct mach_timebase_info info; ret = mach_timebase_info(&info); if(!is_error(ret)) { struct mach_timebase_info *outInfo = (void*)arg1; outInfo->numer = tswap32(info.numer); outInfo->denom = tswap32(info.denom); } break; case -90: DPRINTF("mach_wait_until()\n"); extern int mach_wait_until(uint64_t); // XXX: is there any header for that? ret = mach_wait_until(((uint64_t)arg2<<32) | (uint64_t)arg1); break; case -91: DPRINTF("mk_timer_create()\n"); extern int mk_timer_create(); // XXX: is there any header for that? ret = mk_timer_create(); break; case -92: DPRINTF("mk_timer_destroy()\n"); extern int mk_timer_destroy(int); // XXX: is there any header for that? ret = mk_timer_destroy(arg1); break; case -93: DPRINTF("mk_timer_create()\n"); extern int mk_timer_arm(int, uint64_t); // XXX: is there any header for that? ret = mk_timer_arm(arg1, ((uint64_t)arg3<<32) | (uint64_t)arg2); break; case -94: DPRINTF("mk_timer_cancel()\n"); extern int mk_timer_cancel(int, uint64_t *); // XXX: is there any header for that? ret = mk_timer_cancel(arg1, (uint64_t *)arg2); if((!is_error(ret)) && arg2) tswap64s((uint64_t *)arg2); break; default: gemu_log("qemu: Unsupported mach syscall: %d(0x%x)\n", num, num); gdb_handlesig (cpu_env, SIGTRAP); exit(0); break; } return ret; }
static inline void bswap_log2phys(struct log2phys *f) { tswap32s(&f->l2p_flags); tswap64s(&f->l2p_contigbytes); tswap64s(&f->l2p_devoffset); }
static inline void bswap_fbootstraptransfer(struct fbootstraptransfer *f) { tswap64s(&f->fbt_offset); tswap32s((uint32_t*)&f->fbt_length); tswap32s((uint32_t*)&f->fbt_buffer); /* XXX: this is a ptr */ }
static inline void bswap_radvisory(struct radvisory *f) { tswap64s(&f->ra_offset); tswap32s(&f->ra_count); }