/**
* Initializes the UART uDMA settings
**/
void twe_initUARTtxUDMA(void) {
#ifdef PART_TM4C1294NCPDT // EK-TM4C1294XL
uDMAChannelAssign(UDMA_CH11_UART6TX);
#endif
UARTIntEnable(TWE_UART_COMM_BASE, UART_INT_TX);
// Place the uDMA channel attributes in a known state. These should already be disabled by default.
uDMAChannelAttributeDisable(TWE_UART_COMM_UDMA_CHANNEL ,
UDMA_ATTR_USEBURST | UDMA_ATTR_ALTSELECT |
(UDMA_ATTR_HIGH_PRIORITY |
UDMA_ATTR_REQMASK));
// Configure the control parameters for the UART0 TX channel. The channel
// will be used to send the output data
uDMAChannelControlSet(TWE_UART_COMM_UDMA_CHANNEL | UDMA_PRI_SELECT,
UDMA_SIZE_8 | UDMA_SRC_INC_8 | UDMA_DST_INC_NONE |
UDMA_ARB_8);
// Set up the transfer parameters for the UART0 Tx channel. This will
// configure the transfer buffer and the transfer size.
uDMAChannelTransferSet(TWE_UART_COMM_UDMA_CHANNEL | UDMA_PRI_SELECT,
UDMA_MODE_AUTO,
(void *)twe_g_UARTtxBufferPRI, (void *)(TWE_UART_COMM_BASE + UART_O_DR),
TWE_UART_TX_BUFFER_LENGTH);
uDMAChannelAttributeEnable(TWE_UART_COMM_UDMA_CHANNEL , UDMA_ATTR_REQMASK);
// Now the software channel is primed to start a transfer. The channel
// must be enabled. For software based transfers, a request must be
// issued. After this, the uDMA memory transfer begins.
//uDMAChannelEnable(UDMA_CHANNEL_UART0TX | UART_INT_FE);
//IntEnable(INT_UDMA); // Enables the Software channel interrupt that triggers
// upon completion of a software transfer.
}
/**
* Initializes the QSSI RTX uDMA to transfer 4 bytes from memory to the QSSI TX FIFO
**/
void twe_initQSSIuDMAtx(void) {
SSIDMAEnable(twe_QSSI_COMM_BASE, SSI_DMA_TX);
uDMAChannelAssign(twe_QSSI_COMM_TX_UDMA_CHANNEL_ASSIGN);
// Place the uDMA channel attributes in a known state. These should already be disabled by default.
uDMAChannelAttributeDisable(twe_QSSI_COMM_TX_UDMA_CHANNEL,
UDMA_ATTR_USEBURST | UDMA_ATTR_ALTSELECT |
(UDMA_ATTR_HIGH_PRIORITY |
UDMA_ATTR_REQMASK));
// Configure the control parameters for the SSI2 RX channel. The channel
// will be used to transfer the ADC measurements to memory.
uDMAChannelControlSet(twe_QSSI_COMM_TX_UDMA_CHANNEL | UDMA_PRI_SELECT,
UDMA_SIZE_8 | UDMA_SRC_INC_8 | UDMA_DST_INC_NONE |
UDMA_ARB_4);
// Set up the transfer parameters for the SSI2 Rx channel. This will
// configure the transfer buffers and the transfer size.
uDMAChannelTransferSet(twe_QSSI_COMM_TX_UDMA_CHANNEL | UDMA_PRI_SELECT,
UDMA_MODE_BASIC,
(void *)(twe_g_QSSItxBuffer), (void *)(TWE_UART_COMM_BASE + UART_O_DR),
4);
uDMAChannelAttributeEnable(twe_QSSI_COMM_TX_UDMA_CHANNEL, UDMA_ATTR_HIGH_PRIORITY);
//SSIIntEnable(ADC_SSI_BASE, SSI_DMARX);
//IntEnable(ADC_SSI_INT);
uDMAChannelEnable(twe_QSSI_COMM_TX_UDMA_CHANNEL);
}
//*****************************************************************************
//
// Main function, setup DMA and perform flash write. Verify the transaction.
//
//*****************************************************************************
int
main(void)
{
uint16_t i;
int32_t i32Res;
//
// Set the clocking to run directly from the external crystal/oscillator.
// (no ext 32k osc, no internal osc)
//
SysCtrlClockSet(false, false, SYS_CTRL_SYSDIV_32MHZ);
//
// Set IO clock to the same as system clock
//
SysCtrlIOClockSet(SYS_CTRL_SYSDIV_32MHZ);
//
// Set up the serial console to use for displaying messages. This is
// just for this example program and is not needed for Systick operation.
//
InitConsole();
//
// Display the setup on the console.
//
UARTprintf("Example - Write to Flash using DMA.\n");
//
// Erase Flash page that will hold our transferred data
//
i32Res = FlashMainPageErase(PAGE_TO_ERASE_START_ADDR);
ASSERT(i32Res==0);
//
// Fill Source buffer (to be copied to flash) with some data
//
for(i=0; i<256; i++)
{
ucSourceBuffer[i] = '0' + (i % 10);
}
//
// Enable the uDMA controller.
//
uDMAEnable();
//
// Disable the uDMA channel to be used, before modifications are done.
//
uDMAChannelDisable(UDMA_CH2_FLASH);
//
// Set the base for the channel control table.
//
uDMAControlBaseSet(&ucDMAControlTable[0]);
//
// Assign the DMA channel
//
uDMAChannelAssign(UDMA_CH2_FLASH);
//
// Set attributes for the channel.
//
uDMAChannelAttributeDisable(UDMA_CH2_FLASH, UDMA_ATTR_HIGH_PRIORITY);
//
// Now set up the characteristics of the transfer.
// 32-bit data size, with source increments in words (32 bits),
// no destination increment.
// A bus arbitration size of 1 must be used.
//
uDMAChannelControlSet(UDMA_CH2_FLASH, UDMA_SIZE_32 | UDMA_SRC_INC_32 |
UDMA_DST_INC_NONE | UDMA_ARB_1);
//
// Set transfer parameters.
// Source address is the location of the data to write
// and destination address is the FLASH_CTRL_FWDATA register.
//
uDMAChannelTransferSet(UDMA_CH2_FLASH, UDMA_MODE_BASIC, ucSourceBuffer,
(void *) FLASH_CTRL_FWDATA, sizeof(ucSourceBuffer));
//
// Asure that the flash controller is not busy.
//
while(HWREG(FLASH_CTRL_FCTL) & FLASH_CTRL_FCTL_BUSY)
{
}
//
// Initialize Flash control register without changing the cache mode.
//
HWREG(FLASH_CTRL_FCTL) &= FLASH_CTRL_FCTL_CM_M;
//
// Setup Flash Address register to address of first data word (32-bit)
//
HWREG(FLASH_CTRL_FADDR) = PAGE_TO_ERASE_START_ADDR;
//
// Finally, the DMA channel must be enabled.
//
uDMAChannelEnable(UDMA_CH2_FLASH);
//
// Set FCTL.WRITE, to trigger flash write
//
HWREG(FLASH_CTRL_FCTL) |= FLASH_CTRL_FCTL_WRITE;
//
// Wait until all words has been programmed.
//
while( HWREG(FLASH_CTRL_FCTL) & FLASH_CTRL_FCTL_FULL )
{
}
//
// Check if flash write was successfull
//
if (HWREG(FLASH_CTRL_FCTL) & FLASH_CTRL_FCTL_ABORT)
{
UARTprintf("Write not successful!\n");
}
else
{
UARTprintf("Write success!\n");
}
//
// Set control register back to reset value without changing the cache mode.
//
HWREG(FLASH_CTRL_FCTL) &= FLASH_CTRL_FCTL_CM_M;
//
// Compare source buffer and destination flash page
//
if(memcmp(ucSourceBuffer, (void*) PAGE_TO_ERASE_START_ADDR, 256)==0)
{
UARTprintf("Buffer compares to flash page!\n");
}
else
{
UARTprintf("Buffer does not compare to flash page!\n");
}
//
// We are done, loop forever
//
while(1)
{
}
}