void uart_init(int idx) { unsigned int div; div = uart_baudrate_divisor(get_uart_baudrate(), uart_platform_refclk(), uart_input_clock_divider()); sifive_uart_init(uart_platform_baseptr(idx), div); }
void uart_init(int idx) { unsigned int div; div = uart_baudrate_divisor(default_baudrate(), BAUDRATE_REFCLK, BAUDRATE_OVERSAMPLE); uart8250_init(uart_platform_base(idx), div); }
/** * \brief Configure line control settings for UART */ static void a10_uart_configure(struct a10_uart *uart, u32 baud_rate, u8 data_bits, enum uart_parity parity, u8 stop_bits) { u32 reg32; u16 div; div = (u16) uart_baudrate_divisor(baud_rate, uart_platform_refclk(), 16); /* Enable access to Divisor Latch register */ write32(&uart->lcr, UART8250_LCR_DLAB); /* Set baudrate */ write32(&uart->dlh, (div >> 8) & 0xff); write32(&uart->dll, div & 0xff); /* Set line control */ reg32 = (data_bits - 5) & UART8250_LCR_WLS_MSK; switch (parity) { case UART_PARITY_ODD: reg32 |= UART8250_LCR_PEN; break; case UART_PARITY_EVEN: reg32 |= UART8250_LCR_PEN; reg32 |= UART8250_LCR_EPS; break; case UART_PARITY_NONE: /* Fall through */ default: break; } write32(&uart->lcr, reg32); }
void uart_init(int idx) { struct am335x_uart *uart = uart_platform_baseptr(idx); uint16_t div = (uint16_t) uart_baudrate_divisor( default_baudrate(), uart_platform_refclk(), 16); am335x_uart_init(uart, div); }
void uart_init(int idx) { unsigned int div; div = uart_baudrate_divisor(default_baudrate(), uart_platform_refclk(), uart_input_clock_divider()); uart8250_init(uart_platform_base(idx), div); }
void uart_init(int idx) { void *base = uart_platform_baseptr(idx); if (!base) return; unsigned int div; div = uart_baudrate_divisor(default_baudrate(), uart_platform_refclk(), 16); uart8250_mem_init(base, div); }
void uart_init(int idx) { void *base = uart_platform_baseptr(idx); if (!base) return; unsigned int div; div = uart_baudrate_divisor(get_uart_baudrate(), uart_platform_refclk(), uart_input_clock_divider()); uart8250_mem_init(base, div); }