static int z8_txinterrupt(int irq, FAR void *context)
{
struct uart_dev_s *dev = NULL;
struct z8_uart_s *priv;
uint8_t status;
if (g_uart1priv.txirq == irq)
{
dev = &g_uart1port;
}
else if (g_uart0priv.txirq == irq)
{
dev = &g_uart0port;
}
else
{
PANIC(OSERR_INTERNAL);
}
priv = (struct z8_uart_s*)dev->priv;
/* Verify that the transmit data register is empty */
status = z8_getuart(priv, Z8_UART_STAT0);
if (status & Z8_UARTSTAT0_TDRE)
{
/* Handle outgoing, transmit bytes */
uart_xmitchars(dev);
}
return OK;
}
static void z16f_txint(struct uart_dev_s *dev, bool enable)
{
struct z16f_uart_s *priv = (struct z16f_uart_s*)dev->priv;
irqstate_t flags = enter_critical_section();
if (enable)
{
#ifndef CONFIG_SUPPRESS_SERIAL_INTS
up_enable_irq(priv->txirq);
#endif
/* Fake a TX interrupt here by just calling uart_xmitchars() with
* interrupts disabled (note this may recurse).
*/
uart_xmitchars(dev);
}
else
{
up_disable_irq(priv->txirq);
}
priv->txenabled = enable;
leave_critical_section(flags);
}
static int z16f_txinterrupt(int irq, void *context)
{
struct uart_dev_s *dev = NULL;
struct z16f_uart_s *priv;
uint8_t status;
if (g_uart1priv.txirq == irq)
{
dev = &g_uart1port;
}
else if (g_uart0priv.txirq == irq)
{
dev = &g_uart0port;
}
else
{
PANIC();
}
priv = (struct z16f_uart_s*)dev->priv;
/* Verify that the transmit data register is empty */
status = getreg8(priv->uartbase + Z16F_UART_STAT0);
if (status & Z16F_UARTSTAT0_TDRE)
{
/* Handle outgoing, transmit bytes */
uart_xmitchars(dev);
}
return OK;
}
static int up_interrupt(int irq, void *context)
{
struct uart_dev_s *dev;
struct up_dev_s *priv;
uint32_t usr1;
int passes = 0;
dev = up_mapirq(irq);
priv = (struct up_dev_s *)dev->priv;
/* Loop until there are no characters to be transferred or,
* until we have been looping for a long time.
*/
for (; ; )
{
/* Get the current UART status and check for loop
* termination conditions
*/
usr1 = up_serialin(priv, UART_USR1);
usr1 &= (UART_USR1_RRDY | UART_USR1_TRDY);
if (usr1 == 0 || passes > 256)
{
return OK;
}
/* Handline incoming, receive bytes */
if (usr1 & UART_USR1_RRDY)
{
uart_recvchars(dev);
}
/* Handle outgoing, transmit bytes */
if (usr1 & UART_USR1_TRDY &&
(up_serialin(priv, UART_UCR1) & UART_UCR1_TXEMPTYEN) != 0)
{
uart_xmitchars(dev);
}
/* Keep track of how many times we do this in case there
* is some hardware failure condition.
*/
passes++;
}
}
static int usart1_txinterrupt(int irq, void *context)
{
uint8_t ucsr1a = UCSR1A;
/* Handle outgoing, transmit bytes when the transmit data buffer is empty.
* (There may still be data in the shift register).
*/
if ((ucsr1a & (1 << UDRE1)) != 0)
{
/* Transmit data regiser empty ... process outgoing bytes */
uart_xmitchars(&g_usart1port);
}
return OK;
}
static int ez80_interrrupt(int irq, void *context)
{
struct uart_dev_s *dev = NULL;
struct ez80_dev_s *priv;
volatile uint32_t cause;
#ifdef CONFIG_EZ80_UART0
if (g_uart0priv.irq == irq)
{
dev = &g_uart0port;
}
else
#endif
#ifdef CONFIG_EZ80_UART1
if (g_uart1priv.irq == irq)
{
dev = &g_uart1port;
}
else
#endif
{
PANIC();
}
priv = (struct ez80_dev_s*)dev->priv;
cause = ez80_serialin(priv, EZ80_UART_IIR) & EZ80_UARTIIR_CAUSEMASK;
/* Check for character timeout (CTO) or Receiver Data Ready (RDR) */
if (cause == EZ80_UARTINSTS_CTO || cause == EZ80_UARTINSTS_RDR)
{
/* Receive characters from the RX fifo */
uart_recvchars(dev);
}
/* Check for transmission buffer empty */
else if (cause == EZ80_UARTINSTS_TBE)
{
uart_xmitchars(dev);
}
return OK;
}
static void usart1_txint(struct uart_dev_s *dev, bool enable)
{
irqstate_t flags;
/* Enable/disable TX interrupts:
*
* TX: USART Transmit Complete. Set when the entire frame in the Transmit
* Shift Register has been shifted out and there are no new data
* currently present in the transmit buffer.
* DRE: USART Data Register Empty. Indicates if the transmit buffer is ready
* to receive new data: The buffer is empty, and therefore ready to be
* written.
*/
flags = irqsave();
if (enable)
{
/* Set to receive an interrupt when the TX data register is empty */
#ifndef CONFIG_SUPPRESS_SERIAL_INTS
UCSR1B |= (1 << UDRIE1);
// UCSR1B |= (1 << TXCIE1);
/* Fake a TX interrupt here by just calling uart_xmitchars() with
* interrupts disabled (note this may recurse).
*/
uart_xmitchars(&g_usart1port);
#endif
}
else
{
/* Disable the TX interrupt */
UCSR1B &= ~((1 << UDRIE1) | (1 << TXCIE1));
}
irqrestore(flags);
}
