static bool udd_ctrl_interrupt(void) { if (!Is_udd_endpoint_interrupt(0)) return false; // No interrupt events on control endpoint // Search event on control endpoint if (Is_udd_setup_received(0)) { // SETUP packet received udd_ctrl_setup_received(); return true; } if (Is_udd_in_sent(0)) { // IN packet sent udd_ctrl_in_sent(); return true; } if (Is_udd_bank0_received(0)) { // OUT packet received udd_ctrl_out_received(); return true; } if (Is_udd_stall(0)) { // STALLed udd_ack_stall(0); return true; } return false; }
static void udd_ctrl_setup_received(void) { irqflags_t flags; if (UDD_EPCTRL_SETUP != udd_ep_control_state) { // May be a hidden DATA or ZLP phase // or protocol abort udd_ctrl_endofrequest(); // Reinitializes control endpoint management udd_ctrl_init(); } // Fill setup request structure if (8 != udd_udesc_get_buf0_ctn(0)) { udd_ctrl_stall_data(); udd_ack_setup_received(0); return; // Error data number doesn't correspond to SETUP packet } memcpy((uint8_t *) & udd_g_ctrlreq.req, udd_ctrl_buffer, 8); // Manage LSB/MSB to fit with CPU usage udd_g_ctrlreq.req.wValue = le16_to_cpu(udd_g_ctrlreq.req.wValue); udd_g_ctrlreq.req.wIndex = le16_to_cpu(udd_g_ctrlreq.req.wIndex); udd_g_ctrlreq.req.wLength = le16_to_cpu(udd_g_ctrlreq.req.wLength); // Decode setup request if (udc_process_setup() == false) { // Setup request unknown then stall it udd_ctrl_stall_data(); udd_ack_setup_received(0); return; } udd_ack_setup_received(0); if (Udd_setup_is_in()) { // IN data phase requested udd_ctrl_prev_payload_nb_trans = 0; udd_ctrl_payload_nb_trans = 0; udd_ep_control_state = UDD_EPCTRL_DATA_IN; udd_ctrl_in_sent(); // Send first data transfer } else { if (0 == udd_g_ctrlreq.req.wLength) { // No data phase requested // Send IN ZLP to ACK setup request udd_ctrl_send_zlp_in(); return; } // OUT data phase requested udd_ctrl_prev_payload_nb_trans = 0; udd_ctrl_payload_nb_trans = 0; udd_ep_control_state = UDD_EPCTRL_DATA_OUT; // To detect a protocol error, enable nak interrupt on data IN phase udd_ack_nak_in(0); flags = cpu_irq_save(); udd_enable_nak_in_interrupt(0); cpu_irq_restore(flags); } }
static void udd_ctrl_setup_received(void) { uint8_t i; if (UDD_EPCTRL_SETUP != udd_ep_control_state) { // May be a hidden DATA or ZLP phase // or protocol abort udd_ctrl_endofrequest(); // Reinitializes control endpoint management udd_ctrl_init(); } // Fill setup request structure if (8 != udd_byte_count(0)) { udd_ack_setup_received(0); udd_ctrl_stall_data(); return; // Error data number doesn't correspond to SETUP packet } for (i = 0; i < 8; i++) { ((uint8_t *) & udd_g_ctrlreq.req)[i] = udd_endpoint_fifo_read(0); } // Manage LSB/MSB to fit with CPU usage udd_g_ctrlreq.req.wValue = le16_to_cpu(udd_g_ctrlreq.req.wValue); udd_g_ctrlreq.req.wIndex = le16_to_cpu(udd_g_ctrlreq.req.wIndex); udd_g_ctrlreq.req.wLength = le16_to_cpu(udd_g_ctrlreq.req.wLength); // Decode setup request if (udc_process_setup() == false) { // Setup request unknown then stall it udd_ack_setup_received(0); udd_ctrl_stall_data(); return; } if (Udd_setup_is_in()) { // Set DIR udd_set_endpoint_direction_in(0); udd_ack_setup_received(0); // IN data phase requested udd_ctrl_prev_payload_nb_trans = 0; udd_ctrl_payload_nb_trans = 0; udd_ep_control_state = UDD_EPCTRL_DATA_IN; udd_ctrl_in_sent(); // Send first data transfer } else { udd_ack_setup_received(0); if (0 == udd_g_ctrlreq.req.wLength) { // No data phase requested // Send IN ZLP to ACK setup request udd_ctrl_send_zlp_in(); return; } // OUT data phase requested udd_ctrl_prev_payload_nb_trans = 0; udd_ctrl_payload_nb_trans = 0; udd_ep_control_state = UDD_EPCTRL_DATA_OUT; } }
static void udd_ctrl_setup_received(void) { if (UDD_EPCTRL_SETUP != udd_ep_control_state) { if ((UDD_EPCTRL_HANDSHAKE_WAIT_IN_ZLP == udd_ep_control_state) || (UDD_EPCTRL_HANDSHAKE_WAIT_OUT_ZLP == udd_ep_control_state)) { // Accept that ZLP event can be hidden by setup packet event // in case of setup packet sending quickly after a ZLP udd_ctrl_endofrequest(); } // Reinitializes control endpoint management udd_ctrl_init(); } // Fill setup request structure if (8 != udd_control_out_get_bytecnt()) return; // Error data number don't correspond to SETUP packet memcpy((uint8_t *) & udd_g_ctrlreq.req, udd_ctrl_buffer, 8); // To detect a protocol error on setup, enable nak interrupt on IN/OUT of control endpoint udd_enable_overflow_interrupt(); udd_enable_underflow_interrupt(); // Decode setup request if (udc_process_setup() == false) { // Setup request unknown then stall it udd_ctrl_stall_data(); return; } if (Udd_setup_is_in()) { udd_ctrl_prev_payload_nb_trans = 0; udd_ctrl_payload_nb_trans = 0; udd_ep_control_state = UDD_EPCTRL_DATA_IN; udd_ctrl_in_sent(); // Send first data transfer } else { if (0 == udd_g_ctrlreq.req.wLength) { // No data phase requested // Send IN ZLP to ACK setup request udd_ctrl_send_zlp_in(); return; } // OUT data phase requested udd_ctrl_prev_payload_nb_trans = 0; udd_ctrl_payload_nb_trans = 0; udd_ep_control_state = UDD_EPCTRL_DATA_OUT; // Clear packet to receive first packet udd_control_out_clear_NACK0(); udd_control_out_ack_tc(); } }
static bool udd_ctrl_interrupt(void) { if (!Is_udd_endpoint_interrupt(0)) { return false; // No interrupt events on control endpoint } dbg_print("0: "); // By default disable overflow and underflow interrupt udd_disable_nak_in_interrupt(0); udd_disable_nak_out_interrupt(0); // Search event on control endpoint if (Is_udd_setup_received(0)) { dbg_print("stup "); // SETUP packet received udd_ctrl_setup_received(); return true; } if (Is_udd_in_send(0) && Is_udd_in_send_interrupt_enabled(0)) { dbg_print("in "); // IN packet sent udd_ctrl_in_sent(); return true; } if (Is_udd_out_received(0)) { dbg_print("out "); // OUT packet received udd_ctrl_out_received(); return true; } if (Is_udd_nak_out(0)) { dbg_print("nako "); // Overflow on OUT packet udd_ack_nak_out(0); udd_ctrl_overflow(); return true; } if (Is_udd_nak_in(0)) { dbg_print("naki "); // Underflow on IN packet udd_ack_nak_in(0); udd_ctrl_underflow(); return true; } dbg_print("n%x ", (int)UHDP_ARRAY(UOTGHS_DEVEPTISR[0], 0)); return false; }
static bool udd_ctrl_interrupt(void) { if (!Is_udd_endpoint_interrupt(0)) return false; // No interrupt events on control endpoint // By default disable overflow and underflow interrupt udd_disable_nak_in_interrupt(0); udd_disable_nak_out_interrupt(0); // Search event on control endpoint if (Is_udd_setup_received(0)) { // SETUP packet received udd_ctrl_setup_received(); return true; } if (Is_udd_in_send(0) && Is_udd_in_send_interrupt_enabled(0)) { // IN packet sent udd_ctrl_in_sent(); return true; } if (Is_udd_out_received(0)) { // OUT packet received udd_ctrl_out_received(); return true; } if (Is_udd_nak_out(0)) { // Overflow on OUT packet udd_ack_nak_out(0); udd_ctrl_overflow(); return true; } if (Is_udd_nak_in(0)) { // Underflow on IN packet udd_ack_nak_in(0); udd_ctrl_underflow(); return true; } return false; }
static void udd_ctrl_setup_received(void) { irqflags_t flags; uint8_t i; if (UDD_EPCTRL_SETUP != udd_ep_control_state) { // May be a hidden DATA or ZLP phase // or protocol abort udd_ctrl_endofrequest(); // Reinitializes control endpoint management udd_ctrl_init(); } // Fill setup request structure if (8 != udd_byte_count(0)) { udd_ctrl_stall_data(); udd_ack_setup_received(0); return; // Error data number doesn't correspond to SETUP packet } uint32_t *ptr = (uint32_t *) & udd_get_endpoint_fifo_access(0, 32); for (i = 0; i < 8 / 4; i++) { ((uint32_t *) & udd_g_ctrlreq.req)[i] = *ptr++; } // Manage LSB/MSB to fit with CPU usage udd_g_ctrlreq.req.wValue = le16_to_cpu(udd_g_ctrlreq.req.wValue); udd_g_ctrlreq.req.wIndex = le16_to_cpu(udd_g_ctrlreq.req.wIndex); udd_g_ctrlreq.req.wLength = le16_to_cpu(udd_g_ctrlreq.req.wLength); // Decode setup request if (udc_process_setup() == false) { // Setup request unknow then stall it udd_ctrl_stall_data(); udd_ack_setup_received(0); return; } udd_ack_setup_received(0); if (Udd_setup_is_in()) { // Compute if an IN ZLP must be send after IN data udd_ctrl_payload_need_in_zlp = ((udd_g_ctrlreq.payload_size % USB_DEVICE_EP_CTRL_SIZE) == 0); // IN data phase requested udd_ctrl_prev_payload_nb_trans = 0; udd_ctrl_payload_nb_trans = 0; udd_ep_control_state = UDD_EPCTRL_DATA_IN; udd_ctrl_in_sent(); // Send first data transfer } else { if (0 == udd_g_ctrlreq.req.wLength) { // No data phase requested // Send IN ZLP to ACK setup request udd_ctrl_send_zlp_in(); return; } // OUT data phase requested udd_ctrl_prev_payload_nb_trans = 0; udd_ctrl_payload_nb_trans = 0; udd_ep_control_state = UDD_EPCTRL_DATA_OUT; // To detect a protocol error, enable nak interrupt on data IN phase udd_ack_nak_in(0); flags = cpu_irq_save(); udd_enable_nak_in_interrupt(0); cpu_irq_restore(flags); } }