int ph1_sld8_umc_init(const struct uniphier_board_data *bd)
{
if ((bd->dram_ch0_size == SZ_128M || bd->dram_ch0_size == SZ_256M) &&
(bd->dram_ch1_size == SZ_128M || bd->dram_ch1_size == SZ_256M) &&
bd->dram_freq == 1333 &&
bd->dram_ch0_width == 16 && bd->dram_ch1_width == 16) {
return umc_init_sub(bd->dram_freq,
bd->dram_ch0_size / SZ_128M,
bd->dram_ch1_size / SZ_128M);
} else {
pr_err("Unsupported DDR configuration\n");
return -EINVAL;
}
}
int umc_init(void)
{
return umc_init_sub(CONFIG_DDR_FREQ, CONFIG_SDRAM0_SIZE / 0x08000000,
CONFIG_SDRAM1_SIZE / 0x08000000);
}