/* Read/Write common */
void psion_state::io_rw(address_space &space, UINT16 offset)
{
if (space.debugger_access())
return;
switch (offset & 0xffc0)
{
case 0xc0:
/* switch off, CPU goes into standby mode */
m_enable_nmi = 0;
m_stby_pwr = 1;
space.machine().device<cpu_device>("maincpu")->suspend(SUSPEND_REASON_HALT, 1);
break;
case 0x100:
m_pulse = 1;
break;
case 0x140:
m_pulse = 0;
break;
case 0x200:
m_kb_counter = 0;
break;
case 0x180:
beep_set_state(m_beep, 1);
break;
case 0x1c0:
beep_set_state(m_beep, 0);
break;
case 0x240:
if (offset == 0x260 && (m_rom_bank_count || m_ram_bank_count))
{
m_ram_bank=0;
m_rom_bank=0;
update_banks(machine());
}
else
m_kb_counter++;
break;
case 0x280:
if (offset == 0x2a0 && m_ram_bank_count)
{
m_ram_bank++;
update_banks(machine());
}
else
m_enable_nmi = 1;
break;
case 0x2c0:
if (offset == 0x2e0 && m_rom_bank_count)
{
m_rom_bank++;
update_banks(machine());
}
else
m_enable_nmi = 0;
break;
}
}
/* Read/Write common */
void psion_state::io_rw(address_space &space, uint16_t offset)
{
if (machine().side_effects_disabled())
return;
switch (offset & 0xffc0)
{
case 0xc0:
/* switch off, CPU goes into standby mode */
m_enable_nmi = 0;
m_stby_pwr = 1;
m_maincpu->suspend(SUSPEND_REASON_HALT, 1);
break;
case 0x100:
m_pulse = 1;
break;
case 0x140:
m_pulse = 0;
break;
case 0x200:
m_kb_counter = 0;
break;
case 0x180:
m_beep->set_state(1);
break;
case 0x1c0:
m_beep->set_state(0);
break;
case 0x240:
if (offset == 0x260 && (m_rom_bank_count || m_ram_bank_count))
{
m_ram_bank=0;
m_rom_bank=0;
update_banks();
}
else
m_kb_counter++;
break;
case 0x280:
if (offset == 0x2a0 && m_ram_bank_count)
{
m_ram_bank++;
update_banks();
}
else
m_enable_nmi = 1;
break;
case 0x2c0:
if (offset == 0x2e0 && m_rom_bank_count)
{
m_rom_bank++;
update_banks();
}
else
m_enable_nmi = 0;
break;
}
}
void psion_state::machine_reset()
{
m_enable_nmi=0;
m_kb_counter=0;
m_ram_bank=0;
m_rom_bank=0;
m_pulse=0;
if (m_rom_bank_count || m_ram_bank_count)
update_banks(machine());
}
void nes_benshieng_device::pcb_reset()
{
m_dipsetting = 0;
m_mmc_prg_bank[0] = 0xff;
m_mmc_prg_bank[1] = 0xff;
m_mmc_prg_bank[2] = 0xff;
m_mmc_prg_bank[3] = 0xff;
memset(m_mmc_vrom_bank, 0, sizeof(m_mmc_vrom_bank));
update_banks();
}
void nakajies_state::machine_reset()
{
m_irq_enabled = 0;
m_irq_active = 0;
m_lcd_memory_start = 0;
m_matrix = 0;
/* Initialize banks */
for ( int i = 0; i < 8; i++ )
{
m_bank[i] = 0;
}
update_banks();
}
void nakajies_state::machine_reset()
{
m_irq_enabled = 0;
m_irq_active = 0;
m_lcd_memory_start = 0;
m_matrix = 0;
/* Initialize banks */
for (auto & elem : m_bank)
{
elem = 0;
}
memset(m_ram_base, 0, m_ram_size);
update_banks();
}
