/* initialize the interface */ static rt_err_t rt_dm9161_init(rt_device_t dev) { unsigned int phyid1, phyid2; int detected = -1; unsigned long phy_id; unsigned short phy_address = 0; while ((detected != 0) && (phy_address < 32)) { /* Read the PHY ID registers */ enable_mdi(); read_phy(phy_address, MII_PHYSID1, &phyid1); read_phy(phy_address, MII_PHYSID2, &phyid2); disable_mdi(); phy_id = (phyid1 << 16) | (phyid2 & 0xfff0); switch (phy_id) { case MII_DM9161_ID: /* Davicom 9161: PHY_ID1 = 0x181, PHY_ID2 = B881 */ case MII_DM9161A_ID: /* Davicom 9161A: PHY_ID1 = 0x181, PHY_ID2 = B8A0 */ case MII_RTL8201_ID: /* Realtek RTL8201: PHY_ID1 = 0, PHY_ID2 = 0x8201 */ case MII_BCM5221_ID: /* Broadcom BCM5221: PHY_ID1 = 0x40, PHY_ID2 = 0x61e0 */ case MII_DP83847_ID: /* National Semiconductor DP83847: */ case MII_AC101L_ID: /* Altima AC101L: PHY_ID1 = 0x22, PHY_ID2 = 0x5520 */ case MII_KS8721_ID: /* Micrel KS8721: PHY_ID1 = 0x22, PHY_ID2 = 0x1610 */ { enable_mdi(); #warning SHOULD SET MAC ADDR //get_mac_address(dev); /* Get ethernet address and store it in dev->dev_addr */ update_mac_address(); /* Program ethernet address into MAC */ //用哈希寄存器比较当前群播地址,全双工,添加CRC校验,短数据帧进行填充 sep_emac_write(MAC_CTRL, 0xa413); #warning SHOULD DETERMIN LINK SPEED update_link_speed(phy_address); dm9161_device.phy_addr = phy_address; disable_mdi(); break; } } phy_address++; } rt_dm9161_open(dev,0); return RT_EOK; }
static int sh_eth_dev_init(struct net_device *ndev) { int ret = 0; struct sh_eth_private *mdp = netdev_priv(ndev); u_int32_t rx_int_var, tx_int_var; u32 val; /* Soft Reset */ sh_eth_reset(ndev); /* Descriptor format */ sh_eth_ring_format(ndev); if (mdp->cd->rpadir) sh_eth_write(ndev, mdp->cd->rpadir_value, RPADIR); /* all sh_eth int mask */ sh_eth_write(ndev, 0, EESIPR); #if defined(__LITTLE_ENDIAN__) if (mdp->cd->hw_swap) sh_eth_write(ndev, EDMR_EL, EDMR); else #endif sh_eth_write(ndev, 0, EDMR); /* FIFO size set */ sh_eth_write(ndev, mdp->cd->fdr_value, FDR); sh_eth_write(ndev, 0, TFTR); /* Frame recv control */ sh_eth_write(ndev, mdp->cd->rmcr_value, RMCR); rx_int_var = mdp->rx_int_var = DESC_I_RINT8 | DESC_I_RINT5; tx_int_var = mdp->tx_int_var = DESC_I_TINT2; sh_eth_write(ndev, rx_int_var | tx_int_var, TRSCER); if (mdp->cd->bculr) sh_eth_write(ndev, 0x800, BCULR); /* Burst sycle set */ sh_eth_write(ndev, mdp->cd->fcftr_value, FCFTR); if (!mdp->cd->no_trimd) sh_eth_write(ndev, 0, TRIMD); /* Recv frame limit set register */ sh_eth_write(ndev, RFLR_VALUE, RFLR); sh_eth_write(ndev, sh_eth_read(ndev, EESR), EESR); sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR); /* PAUSE Prohibition */ val = (sh_eth_read(ndev, ECMR) & ECMR_DM) | ECMR_ZPF | (mdp->duplex ? ECMR_DM : 0) | ECMR_TE | ECMR_RE; sh_eth_write(ndev, val, ECMR); if (mdp->cd->set_rate) mdp->cd->set_rate(ndev); /* E-MAC Status Register clear */ sh_eth_write(ndev, mdp->cd->ecsr_value, ECSR); /* E-MAC Interrupt Enable register */ sh_eth_write(ndev, mdp->cd->ecsipr_value, ECSIPR); /* Set MAC address */ update_mac_address(ndev); /* mask reset */ if (mdp->cd->apr) sh_eth_write(ndev, APR_AP, APR); if (mdp->cd->mpr) sh_eth_write(ndev, MPR_MP, MPR); if (mdp->cd->tpauser) sh_eth_write(ndev, TPAUSER_UNLIMITED, TPAUSER); /* Setting the Rx mode will start the Rx process. */ sh_eth_write(ndev, EDRRR_R, EDRRR); netif_start_queue(ndev); return ret; }
static int sh_eth_dev_init(struct net_device *ndev) { int ret = 0; struct sh_eth_private *mdp = netdev_priv(ndev); u32 ioaddr = ndev->base_addr; u_int32_t rx_int_var, tx_int_var; u32 val; /* Soft Reset */ sh_eth_reset(ndev); /* Descriptor format */ sh_eth_ring_format(ndev); ctrl_outl(RPADIR_INIT, ioaddr + RPADIR); /* all sh_eth int mask */ ctrl_outl(0, ioaddr + EESIPR); #if defined(CONFIG_CPU_SUBTYPE_SH7763) ctrl_outl(EDMR_EL, ioaddr + EDMR); #else ctrl_outl(0, ioaddr + EDMR); /* Endian change */ #endif /* FIFO size set */ ctrl_outl((FIFO_SIZE_T | FIFO_SIZE_R), ioaddr + FDR); ctrl_outl(0, ioaddr + TFTR); /* Frame recv control */ ctrl_outl(0, ioaddr + RMCR); rx_int_var = mdp->rx_int_var = DESC_I_RINT8 | DESC_I_RINT5; tx_int_var = mdp->tx_int_var = DESC_I_TINT2; ctrl_outl(rx_int_var | tx_int_var, ioaddr + TRSCER); #if defined(CONFIG_CPU_SUBTYPE_SH7763) /* Burst sycle set */ ctrl_outl(0x800, ioaddr + BCULR); #endif ctrl_outl((FIFO_F_D_RFF | FIFO_F_D_RFD), ioaddr + FCFTR); #if !defined(CONFIG_CPU_SUBTYPE_SH7763) ctrl_outl(0, ioaddr + TRIMD); #endif /* Recv frame limit set register */ ctrl_outl(RFLR_VALUE, ioaddr + RFLR); ctrl_outl(ctrl_inl(ioaddr + EESR), ioaddr + EESR); ctrl_outl((DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff), ioaddr + EESIPR); /* PAUSE Prohibition */ val = (ctrl_inl(ioaddr + ECMR) & ECMR_DM) | ECMR_ZPF | (mdp->duplex ? ECMR_DM : 0) | ECMR_TE | ECMR_RE; ctrl_outl(val, ioaddr + ECMR); /* E-MAC Status Register clear */ ctrl_outl(ECSR_INIT, ioaddr + ECSR); /* E-MAC Interrupt Enable register */ ctrl_outl(ECSIPR_INIT, ioaddr + ECSIPR); /* Set MAC address */ update_mac_address(ndev); /* mask reset */ #if defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7763) ctrl_outl(APR_AP, ioaddr + APR); ctrl_outl(MPR_MP, ioaddr + MPR); ctrl_outl(TPAUSER_UNLIMITED, ioaddr + TPAUSER); #endif #if defined(CONFIG_CPU_SUBTYPE_SH7710) ctrl_outl(BCFR_UNLIMITED, ioaddr + BCFR); #endif /* Setting the Rx mode will start the Rx process. */ ctrl_outl(EDRRR_R, ioaddr + EDRRR); netif_start_queue(ndev); return ret; }
/* * Main thread that does the work, reading from INPUT_PORT * and writing to OUTPUT_PORT */ static int lcore_main(void *arg) { const uintptr_t core_num = (uintptr_t)arg; const unsigned num_cores = rte_lcore_count(); uint16_t startQueue, endQueue; uint16_t q, i, p; const uint16_t quot = (uint16_t)(num_vmdq_queues / num_cores); const uint16_t remainder = (uint16_t)(num_vmdq_queues % num_cores); if (remainder) { if (core_num < remainder) { startQueue = (uint16_t)(core_num * (quot + 1)); endQueue = (uint16_t)(startQueue + quot + 1); } else { startQueue = (uint16_t)(core_num * quot + remainder); endQueue = (uint16_t)(startQueue + quot); } } else { startQueue = (uint16_t)(core_num * quot); endQueue = (uint16_t)(startQueue + quot); } /* vmdq queue idx doesn't always start from zero.*/ startQueue += vmdq_queue_base; endQueue += vmdq_queue_base; printf("Core %u(lcore %u) reading queues %i-%i\n", (unsigned)core_num, rte_lcore_id(), startQueue, endQueue - 1); if (startQueue == endQueue) { printf("lcore %u has nothing to do\n", (unsigned)core_num); return 0; } for (;;) { struct rte_mbuf *buf[MAX_PKT_BURST]; const uint16_t buf_size = sizeof(buf) / sizeof(buf[0]); for (p = 0; p < num_ports; p++) { const uint8_t src = ports[p]; const uint8_t dst = ports[p ^ 1]; /* 0 <-> 1, 2 <-> 3 etc */ if ((src == INVALID_PORT_ID) || (dst == INVALID_PORT_ID)) continue; for (q = startQueue; q < endQueue; q++) { const uint16_t rxCount = rte_eth_rx_burst(src, q, buf, buf_size); if (unlikely(rxCount == 0)) continue; rxPackets[q] += rxCount; for (i = 0; i < rxCount; i++) update_mac_address(buf[i], dst); const uint16_t txCount = rte_eth_tx_burst(dst, q, buf, rxCount); if (txCount != rxCount) { for (i = txCount; i < rxCount; i++) rte_pktmbuf_free(buf[i]); } } } } }