void
main(void)
{
memset(edata, 0, (ulong)end-(ulong)edata);
conf.nmach = 1;
machinit();
confinit();
xinit();
trapinit();
mmuinit();
plan9iniinit();
hwintrinit();
clockinit();
timerinit();
console();
quotefmtinstall();
printinit();
cpuidprint();
print("\nPlan 9 from Bell Labs\n");
procinit0();
initseg();
timersinit();
links();
chandevreset();
pageinit();
swapinit();
sharedseginit();
fpsave(&initfp);
initfp.fpscr = 0;
userinit();
schedinit();
}
// Bootstrap processor starts running C code here.
// Allocate a real stack and switch to it, first
// doing some setup required for memory allocator to work.
int
main(void)
{
kinit1(end, P2V(4*1024*1024)); // phys page allocator
kvmalloc(); // kernel page table
mpinit(); // collect info about this machine
lapicinit();
seginit(); // set up segments
cprintf("\ncpu%d: starting xv6\n\n", cpu->id);
picinit(); // interrupt controller
ioapicinit(); // another interrupt controller
consoleinit(); // I/O devices & their interrupts
uartinit(); // serial port
pinit(); // process table
tvinit(); // trap vectors
binit(); // buffer cache
fileinit(); // file table
ideinit(); // disk
if(!ismp)
timerinit(); // uniprocessor timer
startothers(); // start other processors
kinit2(P2V(4*1024*1024), P2V(PHYSTOP)); // must come after startothers()
userinit(); // first user process
mpmain();
}
// Bootstrap processor starts running C code here.
// Allocate a real stack and switch to it, first
// doing some setup required for memory allocator to work.
int
main(void)
{
kinit1(end, P2V(4*1024*1024)); // phys page allocator // kmem. freelist added
cprintf("%x \n", end);
kvmalloc(); // kernel page table
#ifdef CONFIG_MULTI_PROCESS
mpinit(); // collect info about this machine
#endif
lapicinit();
seginit(); // set up segments
picinit(); // interrupt controller: Programmable Interrupt Controller
#ifdef CONFIG_MULTI_PROCESS
ioapicinit(); // another interrupt controller
#endif
consoleinit(); // I/O devices & their interrupts
uartinit(); // serial port
pinit(); // process table
tvinit(); // trap vectors
binit(); // buffer cache
fileinit(); // file table
iinit(); // inode cache
ideinit(); // disk
if(!ismp)
timerinit(); // uniprocessor timer
#ifdef CONFIG_MULTI_PROCESS
startothers(); // start other processors
kinit2(P2V(4*1024*1024), P2V(PHYSTOP)); // must come after startothers()
#endif
userinit(); // first user process
// Finish setting up this processor in mpmain.
mpmain();
}
// Bootstrap processor starts running C code here.
// Allocate a real stack and switch to it, first
// doing some setup required for memory allocator to work.
int
main(void)
{
kinit1(end, P2V(4*1024*1024)); // phys page allocator
kvmalloc(); // kernel page table
mpinit(); // detect other processors
lapicinit(); // interrupt controller
seginit(); // segment descriptors
cprintf("\ncpu%d: starting xv6\n\n", cpunum());
picinit(); // another interrupt controller
ioapicinit(); // another interrupt controller
consoleinit(); // console hardware
uartinit(); // serial port
pinit(); // process table
tvinit(); // trap vectors
binit(); // buffer cache
fileinit(); // file table
ideinit(); // disk
if(!ismp)
timerinit(); // uniprocessor timer
startothers(); // start other processors
kinit2(P2V(4*1024*1024), P2V(PHYSTOP)); // must come after startothers()
userinit(); // first user process
mpmain(); // finish this processor's setup
init_semaphores_on_boot();
}
// Bootstrap processor starts running C code here.
// Allocate a real stack and switch to it, first
// doing some setup required for memory allocator to work.
int
main(void)
{
unsigned char FB[]="MESSAGE WRITTEN THROUGH FRAMEBUFFER!!";
fb_init(); // initialize framebuffer device (2015.11.02)
cprintf("\nUsing Framebuffer still presents some problems :(\n\n");
cprintf("\nSuggestion: review the way it is used in console.c\n\n");
fb_write(FB, sizeof(FB)); // Framebuffer maybe could be used before this moment (2015.11.02)
see_mylock(MYLOCK);
kinit1(end, P2V(4*1024*1024)); // phys page allocator
kvmalloc(); // kernel page table
mpinit(); // collect info about this machine
lapicinit();
seginit(); // set up segments
cprintf("\ncpu%d: starting xv6\n\n", cpu->id);
picinit(); // interrupt controller
ioapicinit(); // another interrupt controller
consoleinit(); // I/O devices & their interrupts
uartinit(); // serial port
pinit(); // process table
tvinit(); // trap vectors
binit(); // buffer cache
fileinit(); // file table
ideinit(); // disk
if(!ismp)
timerinit(); // uniprocessor timer
startothers(); // start other processors
kinit2(P2V(4*1024*1024), P2V(PHYSTOP)); // must come after startothers()
userinit(); // first user process
// Finish setting up this processor in mpmain.
mpmain();
}
// Bootstrap processor starts running C code here.
int
main(int memsize)
{
mpinit(); // collect info about this machine
lapicinit(mpbcpu());
ksegment();
picinit(); // interrupt controller
ioapicinit(); // another interrupt controller
consoleinit(); // I/O devices & their interrupts
uartinit(); // serial port
cprintf("cpus %p cpu %p\n", cpus, cpu);
cprintf("\ncpu%d: starting xv6\n\n", cpu->id);
cprintf("mem: %d kb\n", memsize);
kinit(memsize); // physical memory allocator
pinit(); // process table
tvinit(); // trap vectors
binit(); // buffer cache
fileinit(); // file table
iinit(); // inode cache
ideinit(); // disk
if(!ismp)
timerinit(); // uniprocessor timer
pageinit(); // enable paging
userinit(); // first user process
bootothers(); // start other processors
// Finish setting up this processor in mpmain.
mpmain();
}
// Bootstrap processor starts running C code here.
// Allocate a real stack and switch to it, first
// doing some setup required for memory allocator to work.
int
main(void)
{
kvmalloc(); // kernel page table
mpinit(); // collect info about this machine
lapicinit(mpbcpu());
seginit(); // set up segments
cprintf("\ncpu%d: starting xv6\n\n", cpu->id);
picinit(); // interrupt controller
ioapicinit(); // another interrupt controller
consoleinit(); // I/O devices & their interrupts
uartinit(); // serial port
pinit(); // process table
tvinit(); // trap vectors
binit(); // buffer cache
fileinit(); // file table
iinit(); // inode cache
ideinit(); // disk
if(!ismp)
timerinit(); // uniprocessor timer
startothers(); // start other processors (must come before kinit)
kinit(); // initialize memory allocator
userinit(); // first user process (must come after kinit)
// Finish setting up this processor in mpmain.
mpmain();
}
// Bootstrap processor starts running C code here.
// Allocate a real stack and switch to it, first
// doing some setup required for memory allocator to work.
int
main(void)
{
monitor_clear ();
// Print basic system information.
cprintf ("Ensidia\n\n");
cprintf ("Copyright (c) 2013-2014 Fotis Koutoulakis\n");
cprintf ("Based on xv6 by Russ Cox et al, at MIT CSAIL\n");
kinit1(end, P2V(4*1024*1024)); // phys page allocator
kvmalloc(); // kernel page table
mpinit(); // collect info about this machine
lapicinit();
seginit(); // set up segments
cprintf("\ncpu%d: starting xng kernel\n\n", cpu->id);
picinit(); // interrupt controller
ioapicinit(); // another interrupt controller
consoleinit(); // I/O devices & their interrupts
uartinit(); // serial port
pinit(); // process table
tvinit(); // trap vectors
binit(); // buffer cache
fileinit(); // file table
iinit(); // inode cache
ideinit(); // disk
if(!ismp)
timerinit(); // uniprocessor timer
startothers(); // start other processors
kinit2(P2V(4*1024*1024), P2V(PHYSTOP)); // must come after startothers()
userinit(); // first user process
// Finish setting up this processor in mpmain.
mpmain();
}
/*int main(void){*/
void kmain(void){
// vga_init();
// puts((uint8_t*)"Hello kernel world!\n");
/*do some work here, like initialize timer or paging*/
kinit1(end, P2V(4*1024*1024)); // phys page allocator
kvmalloc(); // kernel page table
mpinit(); // collect info about this machine
lapicinit();
// gdt_descriptor();
// puts((uint8_t*)"GDT initialized...\n");
// idt_descriptor();
// puts((uint8_t*)"IDT initialized...\n");
// cprintf("IDT initialized...\n");
seginit(); // set up segments
cprintf("\ncpu%d: starting xv6\n\n", cpu->id);
picinit(); // interrupt controller
ioapicinit(); // another interrupt controller
consoleinit(); // I/O devices & their interrupts
uartinit(); // serial port
pinit(); // process table
tvinit(); // trap vectors
binit(); // buffer cache
fileinit(); // file table
ideinit(); // disk
if(!ismp)
timerinit(); // uniprocessor timer
startothers(); // start other processors
kinit2(P2V(4*1024*1024), P2V(PHYSTOP)); // must come after startothers()
userinit(); // first user process
// Finish setting up this processor in mpmain.
mpmain();
}
void kmain (void)
{
cpu = &cpus[0];
uart_init (P2V(UART0));
init_vmm ();
kpt_freerange (align_up(&end, PT_SZ), P2V_WO(INIT_KERNMAP));
paging_init (INIT_KERNMAP, PHYSTOP);
kmem_init ();
kmem_init2(P2V(INIT_KERNMAP), P2V(PHYSTOP));
trap_init (); // vector table and stacks for models
gic_init(P2V(VIC_BASE)); // arm v2 gic init
uart_enable_rx (); // interrupt for uart
consoleinit (); // console
pinit (); // process (locks)
binit (); // buffer cache
fileinit (); // file table
iinit (); // inode cache
ideinit (); // ide (memory block device)
#ifdef INCLUDE_REMOVED
timer_init (HZ); // the timer (ticker)
#endif
sti ();
userinit(); // first user process
scheduler(); // start running processes
}
void
main(void)
{
cgapost(0);
mach0init();
options();
ioinit();
i8250console();
quotefmtinstall();
screeninit();
print("\nPlan 9\n");
trapinit0();
mmuinit0();
kbdinit();
i8253init();
cpuidentify();
meminit();
confinit();
archinit();
if(!isa20on())
panic("bootstrap didn't leave a20 address line enabled");
xinit();
if(i8237alloc != nil)
i8237alloc();
trapinit();
printinit();
cpuidprint();
mmuinit();
fpsavealloc();
if(arch->intrinit) /* launches other processors on an mp */
arch->intrinit();
timersinit();
mathinit();
kbdenable();
if(arch->clockenable)
arch->clockenable();
procinit0();
initseg();
if(delaylink){
bootlinks();
pcimatch(0, 0, 0);
}else
links();
conf.monitor = 1;
chandevreset();
cgapost(0xcd);
pageinit();
i8253link();
swapinit();
userinit();
active.thunderbirdsarego = 1;
cgapost(0x99);
schedinit();
}
int main (int argc, char *argv[]) {
struct Options opt;
int status;
opt.toclose = 0;
getstacksize(argc, argv, &opt); /* handle option `-s' */
L = lua_open(opt.stacksize); /* create state */
userinit(); /* open libraries */
register_getargs(argv); /* create `getargs' function */
status = handle_argv(argv+1, &opt);
if (opt.toclose)
lua_close(L);
return status;
}
// Bootstrap processor starts running C code here.
// Allocate a real stack and switch to it, first
// doing some setup required for memory allocator to work.
int
main(void)
{
kinit1(end, P2V(4*1024*1024)); // phys page allocator
kvmalloc(); // kernel page table
mpinit(); // collect info about this machine
lapicinit();
seginit(); // set up segments
cprintf("\ncpu%d: starting xv6\n\n", cpu->id);
picinit(); // interrupt controller
ioapicinit(); // another interrupt controller
consoleinit(); // I/O devices & their interrupts
uartinit(); // serial port
initGraphMode();
initDom();
tryOnce();
toggleOn();
pinit(); // process table
toggleOn();
tvinit(); // trap vectors
toggleOn();
binit(); // buffer cache
toggleOn();
fileinit(); // file table
toggleOn();
iinit(); // inode cache
toggleOn();
ideinit(); // disk
toggleOn();
if(!ismp)
timerinit(); // uniprocessor timer
toggleOn();
startothers(); // start other processors
toggleOn();
kinit2(P2V(4*1024*1024), P2V(PHYSTOP)); // must come after startothers()
toggleOn();
txt_initLock();
mouseEnable();
initProcessMsgMap();
userinit(); // first user process
toggleOn();
endToggle();
// Finish setting up this processor in mpmain.
mpmain();
}
void
main(void)
{
extern char edata[], end[];
uint rev;
okay(1);
m = (Mach*)MACHADDR;
memset(edata, 0, end - edata); /* clear bss */
machinit();
mmuinit1();
optionsinit("/boot/boot boot");
quotefmtinstall();
ataginit((Atag*)BOOTARGS);
confinit(); /* figures out amount of memory */
xinit();
uartconsinit();
screeninit();
print("\nPlan 9 from Bell Labs\n");
rev = getfirmware();
print("firmware: rev %d\n", rev);
if(rev < Minfirmrev){
print("Sorry, firmware (start.elf) must be at least rev %d (%s)\n",
Minfirmrev, Minfirmdate);
for(;;)
;
}
trapinit();
clockinit();
printinit();
timersinit();
cpuidprint();
archreset();
procinit0();
initseg();
links();
chandevreset(); /* most devices are discovered here */
pageinit();
swapinit();
userinit();
gpiomeminit();
schedinit();
assert(0); /* shouldn't have returned */
}
void
main(void)
{
hwrpb = (Hwrpb*)0x10000000;
hwrpb = (Hwrpb*)(KZERO|hwrpb->phys);
arginit();
machinit();
options();
ioinit();
clockinit();
confinit();
archinit();
xinit();
memholes();
if(i8237alloc != nil)
i8237alloc();
mmuinit();
if(arch->coreinit)
arch->coreinit();
trapinit();
screeninit();
printinit();
/* it's now safe to print */
/* dumpopts(); /* DEBUG */
i8250console();
quotefmtinstall();
print("\nPlan 9\n");
cpuidprint();
if(arch->corehello)
arch->corehello();
procinit0();
initseg();
timersinit();
links();
chandevreset();
pageinit();
swapinit();
savefpregs(&initfp);
initfp.fpstatus = 0x68028000;
userinit();
schedinit();
}
void
main(void)
{
machinit();
trapinit();
quotefmtinstall();
confinit();
xinit();
mmuinit();
intrinit();
clockinit();
printinit();
screeninit();
ioinit();
doc("ioinit...");
ns16552install();
poolsizeinit();
doc("ns16552install...");
kbdinit();
doc("kbdinit...");
cacheinit();
doc("cacheinit...");
procinit();
doc("procinit...");
putphys(MID, 0x1F<<16); /* enable arbitration */
links();
doc("links");
chandevreset();
doc("chandevreset...");
print("\nInferno Operating System\n");
print("%s-%s \n\n",VERSION, conffile);
print("JIT Compilation Mode = %d\n",cflag);
userinit();
doc("userinit...");
/* clear pending processor interrupts */
putphys(PROCINTCLR, (~0<<17)|(1<<15));
print("berore schedinit\n");
schedinit();
}
// Os procedimentos de inicialização começam a executar o
// código .C a partir daqui.
// Aloca uma pilha real e troca para ela, primeiro fazendo
// algumas configurações necessárias par o alocador de memória funcionar.
int main(void) {
kinit1(end, P2V(4*1024*1024)); // alocador de páginas de memória física
kvmalloc(); // tabela de páginas do kernel
mpinit(); // detecta outros processadores
lapicinit(); // controlador de interrupções
seginit(); // descritores de segmentos
picinit(); // desabilita pic
ioapicinit(); // outro controlador de interrupções
consoleinit(); // console hardware
uartinit(); // porta serial
pinit(); // tabela de processos
tvinit(); // vetores trap
binit(); // buffer cache
fileinit(); // tabela de arquivo
ideinit(); // disco
startothers(); // inicia outros processadores
kinit2(P2V(4*1024*1024), P2V(PHYSTOP)); // deve vir após startothers()
userinit(); // primeiro processo no modo usuário
mpmain(); // encerra esta configuração de processadores
}
void
main(void)
{
machinit();
options();
archinit();
quotefmtinstall();
confinit();
cpminit();
xinit();
poolsizeinit();
trapinit();
mmuinit();
printinit();
uartinstall();
serialconsole();
doc("screeninit");
screeninit();
doc("kbdinit");
kbdinit();
doc("clockinit");
clockinit();
doc("procinit");
procinit();
cpuidprint();
doc("links");
links();
doc("chandevreset");
chandevreset();
eve = strdup("inferno");
print("\nInferno %s\n", VERSION);
print("Vita Nuova\n");
print("conf %s (%lud) jit %d\n\n",conffile, kerndate, cflag);
doc("userinit");
userinit();
doc("schedinit");
schedinit();
}
/**
* Bootstrap processor starts running C code here.
*/
int main(void)
{
/**
* ld会生成如下几个变量用来标识程序的段
*
* _etext(etext) 正文段结束后第一个地址
* _edata(edata) 数据段结束后第一个地址
* _end(end) bss段结束后第一个地址
*/
extern char edata[], end[];
// clear BSS
memset(edata, 0, end - edata);
// collect info about this machine
mp_init();
lapic_init(mp_bcpu());
cprintf("\ncpu%d: starting myos\n\n", cpu());
cprintf("Welcome to myos !\n");
pinit(); // process table
binit(); // buffer cache
pic_init(); // interrupt controller
ioapic_init(); // another interrupt controller
kinit(); // physical memory allocator
tvinit(); // trap vectors
fileinit(); // file table
iinit(); // inode cache
console_init(); // I/O devices & their interrupts
ide_init(); // disk
if(!ismp)
timer_init(); // uniprocessor timer
userinit(); // first user process
bootothers(); // start other processors
// Finish setting up this processor in mpmain.
mpmain();
}
void
main(void)
{
mmuinvalidate();
/* zero out bss */
memset(edata, 0, end-edata);
/* point to Mach structure */
m = (Mach*)MACHADDR;
memset(m, 0, sizeof(Mach));
m->ticks = 1;
active.machs = 1;
rs232power(1);
quotefmtinstall();
iprint("\nPlan 9 bitsy kernel\n");
confinit();
xinit();
mmuinit();
machinit();
trapinit();
sa1110_uartsetup(1);
dmainit();
screeninit();
printinit(); /* from here on, print works, before this we need iprint */
clockinit();
procinit0();
initseg();
links();
chandevreset();
pageinit();
swapinit();
userinit();
powerinit();
schedinit();
}
// Bootstrap processor starts running C code here.
// Allocate a real stack and switch to it, first
// doing some setup required for memory allocator to work.
int
main(void)
{
kinit1(end, P2V(4*1024*1024)); // phys page allocator
kvmalloc(); // kernel page table
mpinit(); // detect other processors
lapicinit(); // interrupt controller
seginit(); // segment descriptors
picinit(); // disable pic
ioapicinit(); // another interrupt controller
consoleinit(); // console hardware
uartinit(); // serial port
pinit(); // process table
shminit(); // shared memory
tvinit(); // trap vectors
binit(); // buffer cache
fileinit(); // file table
ideinit(); // disk
startothers(); // start other processors
kinit2(P2V(4*1024*1024), P2V(PHYSTOP)); // must come after startothers()
userinit(); // first user process
mpmain(); // finish this processor's setup
}
void
main(u32int ax, u32int bx)
{
vlong hz;
memset(edata, 0, end - edata);
/*
* ilock via i8250enable via i8250console
* needs m->machno, sys->machptr[] set, and
* also 'up' set to nil.
*/
cgapost(sizeof(uintptr)*8);
memset(m, 0, sizeof(Mach));
m->machno = 0;
m->online = 1;
m->nixtype = NIXTC;
sys->machptr[m->machno] = &sys->mach;
m->stack = PTR2UINT(sys->machstk);
m->vsvm = sys->vsvmpage;
up = nil;
active.nonline = 1;
active.exiting = 0;
active.nbooting = 0;
asminit();
multiboot(ax, bx, 0);
options(oargc, oargv);
crapoptions();
/*
* Need something for initial delays
* until a timebase is worked out.
*/
m->cpuhz = 2000000000ll;
m->cpumhz = 2000;
cgainit();
i8250console("0");
consputs = cgaconsputs;
vsvminit(MACHSTKSZ, NIXTC);
conf.nmach = 1;
fmtinit();
print("\nNIX\n");
if(vflag){
print("&ax = %#p, ax = %#ux, bx = %#ux\n", &ax, ax, bx);
multiboot(ax, bx, vflag);
}
m->perf.period = 1;
if((hz = archhz()) != 0ll){
m->cpuhz = hz;
m->cyclefreq = hz;
m->cpumhz = hz/1000000ll;
}
/*
* Mmuinit before meminit because it
* flushes the TLB via m->pml4->pa.
*/
mmuinit();
ioinit();
kbdinit();
meminit();
confinit();
archinit();
mallocinit();
/*
* Acpiinit will cause the first malloc
* call to happen.
* If the system dies here it's probably due
* to malloc not being initialised
* correctly, or the data segment is misaligned
* (it's amazing how far you can get with
* things like that completely broken).
*/
acpiinit();
umeminit();
trapinit();
printinit();
/*
* This is necessary with GRUB and QEMU.
* Without it an interrupt can occur at a weird vector,
* because the vector base is likely different, causing
* havoc. Do it before any APIC initialisation.
*/
i8259init(32);
procinit0();
mpsinit(maxcores);
apiconline();
sipi();
timersinit();
kbdenable();
fpuinit();
psinit(conf.nproc);
initimage();
links();
devtabreset();
pageinit();
swapinit();
userinit();
nixsquids();
testiccs();
print("schedinit...\n");
schedinit();
}
void
main() {
uint j=0,i=0,k=0;
uint rev;
ulong pc;
pc = getpc();
pl011_addr((void *)pc, 1);
pl011_puts("Entered main() at ");
pl011_addr(&main, 0);
pl011_puts(" with SP=");
pl011_addr((void *)getsp(), 0);
pl011_puts(" with SC=");
pl011_addr((void *)getsc(), 0);
pl011_puts(" with CPSR=");
pl011_addr((void *)getcpsr(), 0);
pl011_puts(" with SPSR=");
pl011_addr((void *)getspsr(), 1);
pl011_puts("Clearing Mach: ");
memset(m, 0, sizeof(Mach));
pl011_addr((char *)m, 0); pl011_puts("-");
pl011_addr((char *)(m+1), 1);
pl011_puts("Clearing edata: ");
memset(edata, 0, end-edata);
pl011_addr((char *)&edata, 0); pl011_puts("-");
pl011_addr((char *)&end, 1);
conf.nmach = 1;
quotefmtinstall();
confinit();
mmuinit1();
xinit();
poolinit();
poolsizeinit();
//uartconsinit();
screeninit();
trapinit();
timersinit();
clockinit();
printinit();
swcursorinit();
rev = getfirmware();
print("\nARM %ld MHz id %8.8lux firmware: rev %d, mem: %ld\n"
,(m->cpuhz+500000)/1000000, getcpuid(), rev, conf.topofmem/MB);
print("Inferno OS %s Vita Nuova\n", VERSION);
print("Ported to Raspberry Pi (BCM2835) by LynxLine\n\n");
procinit();
links();
chandevreset();
eve = strdup("inferno");
userinit();
schedinit();
pl011_puts("to inifinite loop\n\n");
for (;;);
}
void
main(void)
{
Proc *savup;
static ulong vfy = Datamagic;
static char novga[] = "\nno vga; serial console only\n";
savup = up;
up = nil;
/* m has been set by l32v.s */
/*
* disable address wraps at 1MB boundaries.
* if we're 9boot, ldecomp.s already did this.
*/
a20init();
mach0init();
// options(); /* we don't get options passed to us */
ioinit();
/* we later call i8250console after plan9.ini has been read */
i8250config("0"); /* configure serial port 0 with defaults */
quotefmtinstall();
fmtinstall('i', eipfmt);
fmtinstall('I', eipfmt);
fmtinstall('E', eipfmt);
fmtinstall('V', eipfmt);
fmtinstall('M', eipfmt);
screeninit(); /* cga setup */
cgapost(0xc);
trapinit0();
mmuinit0();
kbdinit();
i8253init();
cpuidentify();
readlsconf();
meminit();
confinit();
archinit();
xinit();
if(i8237alloc != nil)
i8237alloc(); /* dma (for floppy) init */
trapinit();
printinit();
sanity();
cgapost(1);
/*
* soekris servers have no built-in video but each has a serial port.
* they must see serial output, if any, before cga output because
* otherwise the soekris bios will translate cga output to serial
* output, which will garble serial console output.
*/
pcimatch(nil, 0, 0); /* force scan of pci table */
if (!pcivga) {
screenputs = nil;
uartputs(novga, sizeof novga - 1);
}
print(" %s\n\n", hellomsg);
if (vfy != Datamagic)
panic("data segment incorrectly aligned or loaded");
if (savup)
print("up was non-nil (%#p) upon entry to main; bss wasn't zeroed!\n",
savup);
// xsummary();
cpuidprint();
mmuinit();
if(arch->intrinit) /* launches other processors on an mp */
arch->intrinit();
timersinit();
mathinit();
kbdenable();
/*
* 9loadusb runs much faster if we don't use the clock.
* perhaps we're competing with the bios for the use of it?
*/
if(!noclock && arch->clockenable)
arch->clockenable();
procinit0();
initseg();
if(delaylink){
bootlinks();
pcimatch(0, 0, 0);
}else
links();
conf.monitor = 1;
cgapost(0xcd);
chandevreset();
cgapost(2);
pageinit(); /* must follow xinit, and conf.mem must be populated */
i8253link();
userinit();
active.thunderbirdsarego = 1;
cgapost(0xb0);
schedinit();
}
void
main(int argc, char *argv[])
{
Dir *db;
Lsym *l;
Node *n;
char buf[128], *s;
int pid, i;
char *p;
char afile[512];
argv0 = argv[0];
pid = 0;
aout = "v.out";
quiet = 1;
/* turn off all debugging */
protodebug = 0;
mtype = 0;
ARGBEGIN{
case 'm':
mtype = ARGF();
break;
case 'w':
wtflag = 1;
break;
case 'l':
s = ARGF();
if(s == 0)
usage();
lm[nlm++] = s;
break;
case 'd':
p = ARGF();
if (p == 0)
usage();
while (*p) {
setdbg_opt(*p, 0); /* don't print set message */
p++;
}
break;
case 'k':
kernel++;
break;
case 'q':
quiet = 0;
break;
case 'r':
pid = 1;
remote++;
kernel++;
break;
case 'R':
pid = 1;
rdebug++;
s = ARGF();
if(s == 0)
usage();
remfd = opentty(s, 0);
if(remfd < 0){
fprint(2, "acid: can't open %s: %r\n", s);
exits("open");
}
break;
default:
usage();
}ARGEND
if(argc > 0) {
if(remote || rdebug)
aout = argv[0];
else
if(isnumeric(argv[0])) {
pid = atoi(argv[0]);
sprint(prog, "/proc/%d/text", pid);
aout = prog;
if(argc > 1)
aout = argv[1];
else if(kernel)
aout = mysystem();
}
else {
if(kernel) {
print("-k requires a pid");
kernel = 0;
}
aout = argv[0];
}
} else if(rdebug)
aout = "/386/bpc";
else if(remote)
aout = "/mips/bcarrera";
fmtinstall('x', xfmt);
fmtinstall('L', Lfmt);
fmtinstall('f', gfltconv);
fmtinstall('F', gfltconv);
fmtinstall('g', gfltconv);
fmtinstall('G', gfltconv);
fmtinstall('e', gfltconv);
fmtinstall('E', gfltconv);
Binit(&bioout, 1, OWRITE);
bout = &bioout;
kinit();
initialising = 1;
pushfile(0);
loadvars();
installbuiltin();
if(mtype && machbyname(mtype) == 0)
print("unknown machine %s", mtype);
if (attachfiles(aout, pid) < 0)
varreg(); /* use default register set on error */
acidlib = getenv("ACIDLIB");
if(acidlib == nil){
p = getenv("ROOT");
if(p == nil)
p = "/usr/inferno";
snprint(afile, sizeof(afile)-1, "%s/lib/acid", p);
acidlib = strdup(afile);
}
snprint(afile, sizeof(afile)-1, "%s/port", acidlib);
loadmodule(afile);
for(i = 0; i < nlm; i++) {
if((db = dirstat(lm[i])) != nil) {
free(db);
loadmodule(lm[i]);
} else {
sprint(buf, "%s/%s", acidlib, lm[i]);
loadmodule(buf);
}
}
userinit();
varsym();
l = look("acidmap");
if(l && l->proc) {
n = an(ONAME, ZN, ZN);
n->sym = l;
n = an(OCALL, n, ZN);
execute(n);
}
interactive = 1;
initialising = 0;
line = 1;
setup_os_notify();
for(;;) {
if(setjmp(err)) {
Binit(&bioout, 1, OWRITE);
unwind();
}
stacked = 0;
Bprint(bout, "acid: ");
if(yyparse() != 1)
die();
restartio();
unwind();
}
/* not reached */
}
void
main(void)
{
int machno;
/* entry to main pushed stuff onto the stack. */
// memset(edata, 0, (ulong)end-(ulong)edata);
machno = getpir();
if (machno > 0)
startcpu(machno);
// dcrcompile();
if (dverify != 0x01020304) {
uartlputs("data segment not initialised\n");
panic("data segment not initialised");
}
if (bverify != 0) {
uartlputs("bss segment not zeroed\n");
panic("bss segment not zeroed");
}
mach0init();
archreset();
quotefmtinstall();
optionsinit("/boot/boot boot");
// archconsole();
meminit();
confinit();
mmuinit();
xinit(); /* xinit would print if it could */
trapinit();
qtminit();
ioinit();
uncinit();
printinit();
uartliteconsole();
mainmem->flags |= POOL_ANTAGONISM;
mainmem->panic = mypanic;
ethermedium.maxtu = 1512; /* must be multiple of 4 for temac's dma */
// print("\n\nPlan 9k H\n"); /* already printed by l.s */
plan9iniinit();
timersinit();
clockinit();
dma0init(); /* does not start kprocs; see init0 */
fpuinit();
procinit0();
initseg();
links();
chandevreset();
okprint = 1; /* only now can we print */
barriers();
dcflush((uintptr)&okprint, sizeof okprint);
cpuidprint();
print("%d Hz clock", HZ);
print("; memory size %,ud (%#ux)\n", (uint)memsz, (uint)memsz);
pageinit();
swapinit();
userinit();
active.thunderbirdsarego = 1;
dcflush((uintptr)&active.thunderbirdsarego,
sizeof active.thunderbirdsarego);
schedinit();
/* no return */
panic("schedinit returned");
}
void
main(uint32_t mbmagic, uint32_t mbaddress)
{
Mach *m = entrym;
/* when we get here, entrym is set to core0 mach. */
sys->machptr[m->machno] = m;
// Very special case for BSP only. Too many things
// assume this is set.
wrmsr(GSbase, PTR2UINT(&sys->machptr[m->machno]));
if (machp() != m)
panic("m and machp() are different!!\n");
assert(sizeof(Mach) <= PGSZ);
/*
* Check that our data is on the right boundaries.
* This works because the immediate value is in code.
*/
if (x != 0x123456)
panic("Data is not set up correctly\n");
memset(edata, 0, end - edata);
m = (void *) (KZERO + 1048576 + 11*4096);
sys = (void *) (KZERO + 1048576);
/*
* ilock via i8250enable via i8250console
* needs m->machno, sys->machptr[] set, and
* also 'up' set to nil.
*/
cgapost(sizeof(uintptr_t)*8);
memset(m, 0, sizeof(Mach));
m->machno = 0;
m->online = 1;
m->nixtype = NIXTC;
sys->machptr[m->machno] = &sys->mach;
m->stack = PTR2UINT(sys->machstk);
*(uintptr_t*)m->stack = STACKGUARD;
m->vsvm = sys->vsvmpage;
m->externup = (void *)0;
active.nonline = 1;
active.exiting = 0;
active.nbooting = 0;
asminit();
multiboot(mbmagic, mbaddress, 0);
options(oargc, oargv);
/*
* Need something for initial delays
* until a timebase is worked out.
*/
m->cpuhz = 2000000000ll;
m->cpumhz = 2000;
cgainit();
i8250console("0");
consputs = cgaconsputs;
/* It all ends here. */
vsvminit(MACHSTKSZ, NIXTC, m);
if (machp() != m)
panic("After vsvminit, m and machp() are different");
sys->nmach = 1;
fmtinit();
print("\nHarvey\n");
if(vflag){
multiboot(mbmagic, mbaddress, vflag);
}
m->perf.period = 1;
if((hz = archhz()) != 0ll){
m->cpuhz = hz;
m->cyclefreq = hz;
m->cpumhz = hz/1000000ll;
}
//iprint("archhz returns 0x%lld\n", hz);
//iprint("NOTE: if cpuidhz runs too fast, we get die early with a NULL pointer\n");
//iprint("So, until that's fixed, we bring up AP cores slowly. Sorry!\n");
/*
* Mmuinit before meminit because it
* flushes the TLB via m->pml4->pa.
*/
mmuinit();
ioinit();
meminit();
confinit();
archinit();
mallocinit();
/* test malloc. It's easier to find out it's broken here,
* not deep in some call chain.
* See next note.
*
void *v = malloc(1234);
hi("v "); put64((uint64_t)v); hi("\n");
free(v);
hi("free ok\n");
*/
/*
* Acpiinit will cause the first malloc
* call to happen.
* If the system dies here it's probably due
* to malloc not being initialised
* correctly, or the data segment is misaligned
* (it's amazing how far you can get with
* things like that completely broken).
*/
if (0){ acpiinit(); hi(" acpiinit();\n");}
umeminit();
trapinit();
/*
* This is necessary with GRUB and QEMU.
* Without it an interrupt can occur at a weird vector,
* because the vector base is likely different, causing
* havoc. Do it before any APIC initialisation.
*/
i8259init(32);
procinit0();
mpsinit(maxcores);
apiconline();
/* Forcing to single core if desired */
if(!nosmp) {
sipi();
}
teardownidmap(m);
timersinit();
fpuinit();
psinit(conf.nproc);
initimage();
links();
keybinit();
keybenable();
mouseenable();
devtabreset();
pageinit();
swapinit();
userinit();
/* Forcing to single core if desired */
if(!nosmp) {
nixsquids();
testiccs();
}
print("CPU Freq. %dMHz\n", m->cpumhz);
print("schedinit...\n");
schedinit();
}
// Bootstrap processor starts running C code here.
// Allocate a real stack and switch to it, first
// doing some setup required for memory allocator to work.
int
main(void)
{
monitor_clear();
xylos_logo();
kinit1(end, P2V(4 * 1024 * 1024)); // phys page allocator, 16MB for kernel
kvmalloc(); // kernel page table
mpinit(); // collect info about this machine
lapicinit();
seginit(); // set up segments
cprintf("Initializing interrupts... ");
init_generic_irq_table();
picinit(); // interrupt controller
ioapicinit(); // another interrupt controller
cprintf_color(COLOR_BLACK, COLOR_LIGHT_GREEN, false, "done\n");
cprintf("Initializing console and serial... ");
consoleinit(); // I/O devices & their interrupts
uartinit(); // serial port
cprintf_color(COLOR_BLACK, COLOR_LIGHT_GREEN, false, "done\n");
cprintf("Setting up swap space disk... ");
swapinit();
cprintf_color(COLOR_BLACK, COLOR_LIGHT_GREEN, false, "done\n");
cprintf("Initializing tasking... ");
pinit(); // process table
tvinit(); // trap vectors
binit(); // buffer cache
cprintf_color(COLOR_BLACK, COLOR_LIGHT_GREEN, false, "done\n");
cprintf("Initializing pipe IPC... ");
init_pipe_ipc_system();
if(pipe_ipc_sanitycheck() == 0) {
cprintf_color(COLOR_BLACK, COLOR_LIGHT_GREEN, false, "done\n");
}
cprintf("Initializing direct IPC... ");
init_direct_ipc_table();
if(direct_ipc_sanitycheck() == 0) {
cprintf_color(COLOR_BLACK, COLOR_LIGHT_GREEN, false, "done\n");
}
cprintf("Mounting root filesystem... ");
fileinit(); // file table
ideinit(); // disk
cprintf_color(COLOR_BLACK, COLOR_LIGHT_GREEN, false, "done\n");
if(!ismp) {
cprintf("Starting up uniprocessor CPU... ");
timerinit(); // uniprocessor timer
cprintf_color(COLOR_BLACK, COLOR_LIGHT_GREEN, false, "done\n");
}
if(ismp) {
if(ncpu > 1) {
cprintf("Starting up %d CPU cores... ", ncpu);
} else {
cprintf("Starting up %d CPU core... ", ncpu);
}
}
startothers(); // start other processors
kinit2(P2V(4 * 1024 * 1024), P2V(PHYSTOP)); // 16MB to PHYSTOP [234MB]
if(ismp) {
cprintf_color(COLOR_BLACK, COLOR_LIGHT_GREEN, false, "done\n");
}
// detects and starts km drivers
auto_enable_nic();
// first user process
userinit();
// Finish setting up this processor in mpmain.
mpmain();
}
/*
* at entry, l.s has set m for cpu0 and printed "Plan 9 from Be"
* but has not zeroed bss.
*/
void
main(void)
{
int cpu;
static ulong vfy = 0xcafebabe;
up = nil;
if (vfy != 0xcafebabe) {
serialputc('?');
serialputc('d');
panic("data segment misaligned");
}
memset(edata, 0, end - edata);
/*
* we can't lock until smpon has run, but we're supposed to wait
* until l1 & l2 are on. too bad. l1 is on, l2 will soon be.
*/
smpon();
iprint("ll Labs ");
cacheinit();
/*
* data segment is aligned, bss is zeroed, caches' characteristics
* are known. begin initialisation.
*/
mach0init();
l2pageinit();
mmuinit();
optionsinit("/boot/boot boot");
quotefmtinstall();
/* want plan9.ini to be able to affect memory sizing in confinit */
plan9iniinit(); /* before we step on plan9.ini in low memory */
/* l2 looks for *l2off= in plan9.ini */
l2cache->on(); /* l2->on requires locks to work, thus smpon */
l2cache->info(&cachel[2]);
allcache->on();
cortexa9cachecfg();
trapinit(); /* so confinit can probe memory to size it */
confinit(); /* figures out amount of memory */
/* xinit prints (if it can), so finish up the banner here. */
delay(100);
navailcpus = getncpus();
iprint("(mp arm; %d cpus)\n\n", navailcpus);
delay(100);
for (cpu = 1; cpu < navailcpus; cpu++)
stopcpu(cpu);
xinit();
irqtooearly = 0; /* now that xinit and trapinit have run */
mainmem->flags |= POOL_ANTAGONISM /* | POOL_PARANOIA */ ;
/*
* Printinit will cause the first malloc call.
* (printinit->qopen->malloc) unless any of the
* above (like clockinit) do an irqenable, which
* will call malloc.
* If the system dies here it's probably due
* to malloc(->xalloc) not being initialised
* correctly, or the data segment is misaligned
* (it's amazing how far you can get with
* things like that completely broken).
*
* (Should be) boilerplate from here on.
*/
archreset(); /* cfg clock signals, print cache cfg */
clockinit(); /* start clocks */
timersinit();
delay(50); /* let uart catch up */
printinit();
kbdenable();
cpuidprint();
chkmissing();
procinit0();
initseg();
// dmainit();
links();
conf.monitor = 1;
// screeninit();
iprint("pcireset...");
pcireset(); /* this tends to hang after a reboot */
iprint("ok\n");
chandevreset(); /* most devices are discovered here */
// i8250console(); /* too early; see init0 */
pageinit(); /* prints "1020M memory: ⋯ */
swapinit();
userinit();
/*
* starting a cpu will eventually result in it calling schedinit,
* so everything necessary to run user processes should be set up
* before starting secondary cpus.
*/
launchinit();
/* SMP & FW are already on when we get here; u-boot set them? */
for (cpu = 1; cpu < navailcpus; cpu++)
if (startcpu(cpu) < 0)
panic("cpu%d didn't start", cpu);
l1diag();
schedinit();
panic("cpu%d: schedinit returned", m->machno);
}
/*
* entered from l.s with mmu enabled.
*
* we may have to realign the data segment; apparently 5l -H0 -R4096
* does not pad the text segment. on the other hand, we may have been
* loaded by another kernel.
*
* be careful not to touch the data segment until we know it's aligned.
*/
void
main(Mach* mach)
{
extern char bdata[], edata[], end[], etext[];
static ulong vfy = 0xcafebabe;
m = mach;
if (vfy != 0xcafebabe)
memmove(bdata, etext, edata - bdata);
if (vfy != 0xcafebabe) {
wave('?');
panic("misaligned data segment");
}
memset(edata, 0, end - edata); /* zero bss */
vfy = 0;
wave('9');
machinit();
archreset();
mmuinit();
optionsinit("/boot/boot boot");
quotefmtinstall();
archconsole();
wave(' ');
/* want plan9.ini to be able to affect memory sizing in confinit */
plan9iniinit(); /* before we step on plan9.ini in low memory */
/* set memsize before xinit */
confinit();
/* xinit would print if it could */
xinit();
/*
* Printinit will cause the first malloc call.
* (printinit->qopen->malloc) unless any of the
* above (like clockintr) do an irqenable, which
* will call malloc.
* If the system dies here it's probably due
* to malloc(->xalloc) not being initialised
* correctly, or the data segment is misaligned
* (it's amazing how far you can get with
* things like that completely broken).
*
* (Should be) boilerplate from here on.
*/
trapinit();
clockinit();
printinit();
uartkirkwoodconsole();
/* only now can we print */
print("from Bell Labs\n\n");
#ifdef CRYPTOSANDBOX
print("sandbox: 64K at physical %#lux, mapped to 0xf10b0000\n",
PADDR((uintptr)sandbox & ~(BY2PG-1)));
#endif
archconfinit();
cpuidprint();
timersinit();
procinit0();
initseg();
links();
chandevreset(); /* most devices are discovered here */
spiprobe();
pageinit();
swapinit();
userinit();
schedinit();
panic("schedinit returned");
}
