static void vc4_submit_setup_rcl_render_config_surface(struct vc4_context *vc4, struct drm_vc4_submit_rcl_surface *submit_surf, struct pipe_surface *psurf) { struct vc4_surface *surf = vc4_surface(psurf); if (!surf) { submit_surf->hindex = ~0; return; } struct vc4_resource *rsc = vc4_resource(psurf->texture); submit_surf->hindex = vc4_gem_hindex(vc4, rsc->bo); submit_surf->offset = surf->offset; if (psurf->texture->nr_samples == 0) { submit_surf->bits = VC4_SET_FIELD(vc4_rt_format_is_565(surf->base.format) ? VC4_RENDER_CONFIG_FORMAT_BGR565 : VC4_RENDER_CONFIG_FORMAT_RGBA8888, VC4_RENDER_CONFIG_FORMAT) | VC4_SET_FIELD(surf->tiling, VC4_RENDER_CONFIG_MEMORY_FORMAT); } rsc->writes++; }
static void vc4_submit_setup_rcl_surface(struct vc4_context *vc4, struct drm_vc4_submit_rcl_surface *submit_surf, struct pipe_surface *psurf, bool is_depth, bool is_write) { struct vc4_surface *surf = vc4_surface(psurf); if (!surf) { submit_surf->hindex = ~0; return; } struct vc4_resource *rsc = vc4_resource(psurf->texture); submit_surf->hindex = vc4_gem_hindex(vc4, rsc->bo); submit_surf->offset = surf->offset; if (psurf->texture->nr_samples == 0) { if (is_depth) { submit_surf->bits = VC4_SET_FIELD(VC4_LOADSTORE_TILE_BUFFER_ZS, VC4_LOADSTORE_TILE_BUFFER_BUFFER); } else { submit_surf->bits = VC4_SET_FIELD(VC4_LOADSTORE_TILE_BUFFER_COLOR, VC4_LOADSTORE_TILE_BUFFER_BUFFER) | VC4_SET_FIELD(vc4_rt_format_is_565(psurf->format) ? VC4_LOADSTORE_TILE_BUFFER_BGR565 : VC4_LOADSTORE_TILE_BUFFER_RGBA8888, VC4_LOADSTORE_TILE_BUFFER_FORMAT); } submit_surf->bits |= VC4_SET_FIELD(surf->tiling, VC4_LOADSTORE_TILE_BUFFER_TILING); } else { assert(!is_write); submit_surf->flags |= VC4_SUBMIT_RCL_SURFACE_READ_IS_FULL_RES; } if (is_write) rsc->writes++; }
static void vc4_clear(struct pipe_context *pctx, unsigned buffers, const union pipe_color_union *color, double depth, unsigned stencil) { struct vc4_context *vc4 = vc4_context(pctx); struct vc4_job *job = vc4_get_job_for_fbo(vc4); /* We can't flag new buffers for clearing once we've queued draws. We * could avoid this by using the 3d engine to clear. */ if (job->draw_calls_queued) { perf_debug("Flushing rendering to process new clear.\n"); vc4_job_submit(vc4, job); job = vc4_get_job_for_fbo(vc4); } if (buffers & PIPE_CLEAR_COLOR0) { struct vc4_resource *rsc = vc4_resource(vc4->framebuffer.cbufs[0]->texture); uint32_t clear_color; if (vc4_rt_format_is_565(vc4->framebuffer.cbufs[0]->format)) { /* In 565 mode, the hardware will be packing our color * for us. */ clear_color = pack_rgba(PIPE_FORMAT_R8G8B8A8_UNORM, color->f); } else { /* Otherwise, we need to do this packing because we * support multiple swizzlings of RGBA8888. */ clear_color = pack_rgba(vc4->framebuffer.cbufs[0]->format, color->f); } job->clear_color[0] = job->clear_color[1] = clear_color; rsc->initialized_buffers |= (buffers & PIPE_CLEAR_COLOR0); } if (buffers & PIPE_CLEAR_DEPTHSTENCIL) { struct vc4_resource *rsc = vc4_resource(vc4->framebuffer.zsbuf->texture); unsigned zsclear = buffers & PIPE_CLEAR_DEPTHSTENCIL; /* Clearing ZS will clear both Z and stencil, so if we're * trying to clear just one then we need to draw a quad to do * it instead. */ if ((zsclear == PIPE_CLEAR_DEPTH || zsclear == PIPE_CLEAR_STENCIL) && (rsc->initialized_buffers & ~(zsclear | job->cleared)) && util_format_is_depth_and_stencil(vc4->framebuffer.zsbuf->format)) { perf_debug("Partial clear of Z+stencil buffer, " "drawing a quad instead of fast clearing\n"); vc4_blitter_save(vc4); util_blitter_clear(vc4->blitter, vc4->framebuffer.width, vc4->framebuffer.height, 1, zsclear, NULL, depth, stencil); buffers &= ~zsclear; if (!buffers) return; } /* Though the depth buffer is stored with Z in the high 24, * for this field we just need to store it in the low 24. */ if (buffers & PIPE_CLEAR_DEPTH) { job->clear_depth = util_pack_z(PIPE_FORMAT_Z24X8_UNORM, depth); } if (buffers & PIPE_CLEAR_STENCIL) job->clear_stencil = stencil; rsc->initialized_buffers |= zsclear; } job->draw_min_x = 0; job->draw_min_y = 0; job->draw_max_x = vc4->framebuffer.width; job->draw_max_y = vc4->framebuffer.height; job->cleared |= buffers; job->resolve |= buffers; vc4_start_draw(vc4); }
static void vc4_setup_rcl(struct vc4_context *vc4) { struct vc4_surface *csurf = vc4_surface(vc4->framebuffer.cbufs[0]); struct vc4_resource *ctex = csurf ? vc4_resource(csurf->base.texture) : NULL; struct vc4_surface *zsurf = vc4_surface(vc4->framebuffer.zsbuf); struct vc4_resource *ztex = zsurf ? vc4_resource(zsurf->base.texture) : NULL; if (!csurf) vc4->resolve &= ~PIPE_CLEAR_COLOR0; if (!zsurf) vc4->resolve &= ~(PIPE_CLEAR_DEPTH | PIPE_CLEAR_STENCIL); uint32_t resolve_uncleared = vc4->resolve & ~vc4->cleared; uint32_t width = vc4->framebuffer.width; uint32_t height = vc4->framebuffer.height; uint32_t stride_in_tiles = align(width, 64) / 64; assert(vc4->draw_min_x != ~0 && vc4->draw_min_y != ~0); uint32_t min_x_tile = vc4->draw_min_x / 64; uint32_t min_y_tile = vc4->draw_min_y / 64; uint32_t max_x_tile = (vc4->draw_max_x - 1) / 64; uint32_t max_y_tile = (vc4->draw_max_y - 1) / 64; uint32_t xtiles = max_x_tile - min_x_tile + 1; uint32_t ytiles = max_y_tile - min_y_tile + 1; #if 0 fprintf(stderr, "RCL: resolve 0x%x clear 0x%x resolve uncleared 0x%x\n", vc4->resolve, vc4->cleared, resolve_uncleared); #endif uint32_t reloc_size = 9; uint32_t clear_size = 14; uint32_t config_size = 11 + reloc_size; uint32_t loadstore_size = 7 + reloc_size; uint32_t tilecoords_size = 3; uint32_t branch_size = 5 + reloc_size; uint32_t color_store_size = 1; uint32_t semaphore_size = 1; cl_ensure_space(&vc4->rcl, clear_size + config_size + loadstore_size + semaphore_size + xtiles * ytiles * (loadstore_size * 4 + tilecoords_size * 3 + branch_size + color_store_size)); if (vc4->cleared) { cl_u8(&vc4->rcl, VC4_PACKET_CLEAR_COLORS); cl_u32(&vc4->rcl, vc4->clear_color[0]); cl_u32(&vc4->rcl, vc4->clear_color[1]); cl_u32(&vc4->rcl, vc4->clear_depth); cl_u8(&vc4->rcl, vc4->clear_stencil); } /* The rendering mode config determines the pointer that's used for * VC4_PACKET_STORE_MS_TILE_BUFFER address computations. The kernel * could handle a no-relocation rendering mode config and deny those * packets, but instead we just tell the kernel we're doing our color * rendering to the Z buffer, and just don't emit any of those * packets. */ struct vc4_surface *render_surf = csurf ? csurf : zsurf; struct vc4_resource *render_tex = vc4_resource(render_surf->base.texture); cl_start_reloc(&vc4->rcl, 1); cl_u8(&vc4->rcl, VC4_PACKET_TILE_RENDERING_MODE_CONFIG); cl_reloc(vc4, &vc4->rcl, render_tex->bo, render_surf->offset); cl_u16(&vc4->rcl, width); cl_u16(&vc4->rcl, height); cl_u16(&vc4->rcl, ((render_surf->tiling << VC4_RENDER_CONFIG_MEMORY_FORMAT_SHIFT) | (vc4_rt_format_is_565(render_surf->base.format) ? VC4_RENDER_CONFIG_FORMAT_BGR565 : VC4_RENDER_CONFIG_FORMAT_RGBA8888))); /* The tile buffer normally gets cleared when the previous tile is * stored. If the clear values changed between frames, then the tile * buffer has stale clear values in it, so we have to do a store in * None mode (no writes) so that we trigger the tile buffer clear. * * Excess clearing is only a performance cost, since per-tile contents * will be loaded/stored in the loop below. */ if (vc4->cleared & (PIPE_CLEAR_COLOR0 | PIPE_CLEAR_DEPTH | PIPE_CLEAR_STENCIL)) { cl_u8(&vc4->rcl, VC4_PACKET_TILE_COORDINATES); cl_u8(&vc4->rcl, 0); cl_u8(&vc4->rcl, 0); cl_u8(&vc4->rcl, VC4_PACKET_STORE_TILE_BUFFER_GENERAL); cl_u16(&vc4->rcl, VC4_LOADSTORE_TILE_BUFFER_NONE); cl_u32(&vc4->rcl, 0); /* no address, since we're in None mode */ } uint32_t color_hindex = ctex ? vc4_gem_hindex(vc4, ctex->bo) : 0; uint32_t depth_hindex = ztex ? vc4_gem_hindex(vc4, ztex->bo) : 0; uint32_t tile_alloc_hindex = vc4_gem_hindex(vc4, vc4->tile_alloc); for (int y = min_y_tile; y <= max_y_tile; y++) { for (int x = min_x_tile; x <= max_x_tile; x++) { bool end_of_frame = (x == max_x_tile && y == max_y_tile); bool coords_emitted = false; /* Note that the load doesn't actually occur until the * tile coords packet is processed, and only one load * may be outstanding at a time. */ if (resolve_uncleared & PIPE_CLEAR_COLOR) { vc4_store_before_load(vc4, &coords_emitted); cl_start_reloc(&vc4->rcl, 1); cl_u8(&vc4->rcl, VC4_PACKET_LOAD_TILE_BUFFER_GENERAL); cl_u8(&vc4->rcl, VC4_LOADSTORE_TILE_BUFFER_COLOR | (csurf->tiling << VC4_LOADSTORE_TILE_BUFFER_FORMAT_SHIFT)); cl_u8(&vc4->rcl, vc4_rt_format_is_565(csurf->base.format) ? VC4_LOADSTORE_TILE_BUFFER_BGR565 : VC4_LOADSTORE_TILE_BUFFER_RGBA8888); cl_reloc_hindex(&vc4->rcl, color_hindex, csurf->offset); vc4_tile_coordinates(vc4, x, y, &coords_emitted); } if (resolve_uncleared & (PIPE_CLEAR_DEPTH | PIPE_CLEAR_STENCIL)) { vc4_store_before_load(vc4, &coords_emitted); cl_start_reloc(&vc4->rcl, 1); cl_u8(&vc4->rcl, VC4_PACKET_LOAD_TILE_BUFFER_GENERAL); cl_u8(&vc4->rcl, VC4_LOADSTORE_TILE_BUFFER_ZS | (zsurf->tiling << VC4_LOADSTORE_TILE_BUFFER_FORMAT_SHIFT)); cl_u8(&vc4->rcl, 0); cl_reloc_hindex(&vc4->rcl, depth_hindex, zsurf->offset); vc4_tile_coordinates(vc4, x, y, &coords_emitted); } /* Clipping depends on tile coordinates having been * emitted, so make sure it's happened even if * everything was cleared to start. */ vc4_tile_coordinates(vc4, x, y, &coords_emitted); /* Wait for the binner before jumping to the first * tile's lists. */ if (x == min_x_tile && y == min_y_tile) cl_u8(&vc4->rcl, VC4_PACKET_WAIT_ON_SEMAPHORE); cl_start_reloc(&vc4->rcl, 1); cl_u8(&vc4->rcl, VC4_PACKET_BRANCH_TO_SUB_LIST); cl_reloc_hindex(&vc4->rcl, tile_alloc_hindex, (y * stride_in_tiles + x) * 32); if (vc4->resolve & (PIPE_CLEAR_DEPTH | PIPE_CLEAR_STENCIL)) { vc4_tile_coordinates(vc4, x, y, &coords_emitted); cl_start_reloc(&vc4->rcl, 1); cl_u8(&vc4->rcl, VC4_PACKET_STORE_TILE_BUFFER_GENERAL); cl_u8(&vc4->rcl, VC4_LOADSTORE_TILE_BUFFER_ZS | (zsurf->tiling << VC4_LOADSTORE_TILE_BUFFER_FORMAT_SHIFT)); cl_u8(&vc4->rcl, VC4_STORE_TILE_BUFFER_DISABLE_COLOR_CLEAR); cl_reloc_hindex(&vc4->rcl, depth_hindex, zsurf->offset | ((end_of_frame && !(vc4->resolve & PIPE_CLEAR_COLOR0)) ? VC4_LOADSTORE_TILE_BUFFER_EOF : 0)); coords_emitted = false; } if (vc4->resolve & PIPE_CLEAR_COLOR0) { vc4_tile_coordinates(vc4, x, y, &coords_emitted); if (end_of_frame) { cl_u8(&vc4->rcl, VC4_PACKET_STORE_MS_TILE_BUFFER_AND_EOF); } else { cl_u8(&vc4->rcl, VC4_PACKET_STORE_MS_TILE_BUFFER); } coords_emitted = false; } /* One of the bits needs to have been set that would * have triggered an EOF. */ assert(vc4->resolve & (PIPE_CLEAR_COLOR0 | PIPE_CLEAR_DEPTH | PIPE_CLEAR_STENCIL)); /* Any coords emitted must also have been consumed by * a store. */ assert(!coords_emitted); } } if (vc4->resolve & PIPE_CLEAR_COLOR0) ctex->writes++; if (vc4->resolve & (PIPE_CLEAR_DEPTH | PIPE_CLEAR_STENCIL)) ztex->writes++; }
static void vc4_setup_rcl(struct vc4_context *vc4) { struct vc4_surface *csurf = vc4_surface(vc4->framebuffer.cbufs[0]); struct vc4_resource *ctex = vc4_resource(csurf->base.texture); uint32_t resolve_uncleared = vc4->resolve & ~vc4->cleared; uint32_t width = vc4->framebuffer.width; uint32_t height = vc4->framebuffer.height; uint32_t xtiles = align(width, 64) / 64; uint32_t ytiles = align(height, 64) / 64; #if 0 fprintf(stderr, "RCL: resolve 0x%x clear 0x%x resolve uncleared 0x%x\n", vc4->resolve, vc4->cleared, resolve_uncleared); #endif cl_u8(&vc4->rcl, VC4_PACKET_CLEAR_COLORS); cl_u32(&vc4->rcl, vc4->clear_color[0]); cl_u32(&vc4->rcl, vc4->clear_color[1]); cl_u32(&vc4->rcl, vc4->clear_depth); cl_u8(&vc4->rcl, 0); cl_start_reloc(&vc4->rcl, 1); cl_u8(&vc4->rcl, VC4_PACKET_TILE_RENDERING_MODE_CONFIG); cl_reloc(vc4, &vc4->rcl, ctex->bo, csurf->offset); cl_u16(&vc4->rcl, width); cl_u16(&vc4->rcl, height); cl_u16(&vc4->rcl, ((csurf->tiling << VC4_RENDER_CONFIG_MEMORY_FORMAT_SHIFT) | (vc4_rt_format_is_565(csurf->base.format) ? VC4_RENDER_CONFIG_FORMAT_BGR565 : VC4_RENDER_CONFIG_FORMAT_RGBA8888) | VC4_RENDER_CONFIG_EARLY_Z_COVERAGE_DISABLE)); /* The tile buffer normally gets cleared when the previous tile is * stored. If the clear values changed between frames, then the tile * buffer has stale clear values in it, so we have to do a store in * None mode (no writes) so that we trigger the tile buffer clear. */ if (vc4->cleared & PIPE_CLEAR_COLOR0) { cl_u8(&vc4->rcl, VC4_PACKET_TILE_COORDINATES); cl_u8(&vc4->rcl, 0); cl_u8(&vc4->rcl, 0); cl_u8(&vc4->rcl, VC4_PACKET_STORE_TILE_BUFFER_GENERAL); cl_u16(&vc4->rcl, VC4_LOADSTORE_TILE_BUFFER_NONE); cl_u32(&vc4->rcl, 0); /* no address, since we're in None mode */ } for (int y = 0; y < ytiles; y++) { for (int x = 0; x < xtiles; x++) { bool end_of_frame = (x == xtiles - 1 && y == ytiles - 1); /* Note that the load doesn't actually occur until the * tile coords packet is processed. */ if (resolve_uncleared & PIPE_CLEAR_COLOR) { cl_start_reloc(&vc4->rcl, 1); cl_u8(&vc4->rcl, VC4_PACKET_LOAD_TILE_BUFFER_GENERAL); cl_u8(&vc4->rcl, VC4_LOADSTORE_TILE_BUFFER_COLOR | (csurf->tiling << VC4_LOADSTORE_TILE_BUFFER_FORMAT_SHIFT)); cl_u8(&vc4->rcl, vc4_rt_format_is_565(csurf->base.format) ? VC4_LOADSTORE_TILE_BUFFER_BGR565 : VC4_LOADSTORE_TILE_BUFFER_RGBA8888); cl_reloc(vc4, &vc4->rcl, ctex->bo, csurf->offset); } cl_u8(&vc4->rcl, VC4_PACKET_TILE_COORDINATES); cl_u8(&vc4->rcl, x); cl_u8(&vc4->rcl, y); cl_start_reloc(&vc4->rcl, 1); cl_u8(&vc4->rcl, VC4_PACKET_BRANCH_TO_SUB_LIST); cl_reloc(vc4, &vc4->rcl, vc4->tile_alloc, (y * xtiles + x) * 32); if (vc4->resolve & PIPE_CLEAR_COLOR0) { if (end_of_frame) { cl_u8(&vc4->rcl, VC4_PACKET_STORE_MS_TILE_BUFFER_AND_EOF); } else { cl_u8(&vc4->rcl, VC4_PACKET_STORE_MS_TILE_BUFFER); } } else { assert(!"unfinished: Need to end the frame\n"); } } } }