IRSB *vex_block_bytes(VexArch guest, VexEndness endness, unsigned char *instructions, unsigned long long block_addr, unsigned int num_bytes, int basic_only) { IRSB *sb = NULL; try { unsigned int count = vex_count_instructions(guest, endness, instructions, block_addr, num_bytes, basic_only); sb = vex_block_inst(guest, endness, instructions, block_addr, count); // this is a workaround. Basically, on MIPS, leaving this (the second translation of the same crap) // out leads to exits being dropped in some IRSBs sb = vex_block_inst(guest, endness, instructions, block_addr, count); if (vge.len[0] != num_bytes) { info("vex_block_bytes: only translated %d bytes out of %d in block_addr %x\n", vge.len[0], num_bytes, block_addr); } //assert(vge.len[0] == num_bytes); } catch (VEXError) { last_error = E4C_EXCEPTION.message; } return sb; }
static int pyIRSB_init(pyIRSB *self, PyObject *args, PyObject *kwargs) { if (!kwargs) { self->wrapped = PYVEX_COPYOUT(IRSB, emptyIRSB()); return 0; } PYVEX_WRAP_CONSTRUCTOR(IRSB); #ifdef PYVEX_STATIC unsigned char *bytes = NULL; unsigned int mem_addr = 0; int num_inst = -1; int num_bytes = -1; static char *kwlist[] = {"bytes", "mem_addr", "num_inst", NULL}; if (!PyArg_ParseTupleAndKeywords(args, kwargs, "|s#ii", kwlist, &bytes, &num_bytes, &mem_addr, &num_inst)) return -1; if (num_bytes == 0) { PyErr_SetString(VexException, "No bytes provided"); return -1; } if (num_bytes > 0) { vex_init(); if (num_inst > -1) self->wrapped = vex_block_inst(VexArchAMD64, bytes, mem_addr, num_inst); else self->wrapped = vex_block_bytes(VexArchAMD64, bytes, mem_addr, num_bytes); self->wrapped = PYVEX_COPYOUT(IRSB, self->wrapped); if (self->wrapped == NULL) { PyErr_SetString(VexException, "Error creating IR."); return -1; } return 0; } PyErr_SetString(VexException, "Not enough arguments provided."); return -1; #else PyErr_SetString(VexException, "Statically creating IRSBs is disabled."); return -1; #endif }