static int ov5648_flisclk_ctrl(struct v4l2_subdev *sd, int flag) { static const unsigned int clock_khz = 19200; int ret = 0; #ifdef CONFIG_VLV2_PLAT_CLK if (flag) { ret = vlv2_plat_set_clock_freq(OSC_CAM0_CLK, CLK_19P2MHz); if (ret) return ret; } ret = vlv2_plat_configure_clock(OSC_CAM0_CLK, flag); #endif return ret; }
static int mt9m114_flisclk_ctrl(struct v4l2_subdev *sd, int flag) { #ifdef CONFIG_VLV2_PLAT_CLK if (flag) { int ret; ret = vlv2_plat_set_clock_freq(OSC_CAM0_CLK, OSC_CAM0_CLK); if (ret) return ret; return vlv2_plat_configure_clock(OSC_CAM0_CLK, CLK_ON); } return vlv2_plat_configure_clock(OSC_CAM0_CLK, CLK_OFF); #else pr_err("mt9m114 clock is not set.\n"); return 0; #endif }
static int gc2235f_flisclk_ctrl(struct v4l2_subdev *sd, int flag) { static const unsigned int clock_khz = 19200; int ret = 0; /*if (intel_mid_identify_cpu() != INTEL_MID_CPU_CHIP_VALLEYVIEW2) return intel_scu_ipc_osc_clk(OSC_CLK_CAM1, flag ? clock_khz : 0);*/ #ifdef CONFIG_VLV2_PLAT_CLK if (flag) { ret = vlv2_plat_set_clock_freq(OSC_CAM1_CLK, CLK_19P2MHz); if (ret) return ret; } ret = vlv2_plat_configure_clock(OSC_CAM1_CLK, flag); #endif return ret; }
static int imx175_flisclk_ctrl(struct v4l2_subdev *sd, int flag) { static const unsigned int clock_khz = 19200; #ifdef CONFIG_VLV2_PLAT_CLK if (flag) { int ret; ret = vlv2_plat_set_clock_freq(OSC_CAM0_CLK, CLK_19P2MHz); if (ret) return ret; } return vlv2_plat_configure_clock(OSC_CAM0_CLK, flag); #elif defined(CONFIG_INTEL_SCU_IPC_UTIL) return intel_scu_ipc_osc_clk(OSC_CLK_CAM0, flag ? clock_khz : 0); #else pr_err("imx175 clock is not set\n"); return 0; #endif }
/* * WORKAROUND: * This func will return 0 since MCLK is enabled by BIOS * and will be always on event if set MCLK failed here. * TODO: REMOVE WORKAROUND, err should be returned when * set MCLK failed. */ static int ov2685f_flisclk_ctrl(struct v4l2_subdev *sd, int flag) { static const unsigned int clock_khz = 19200; #ifdef CONFIG_VLV2_PLAT_CLK int ret = 0; if (flag) { ret = vlv2_plat_set_clock_freq(OSC_CAM1_CLK, CLK_19P2MHz); if (ret) pr_err("ov2685f clock set failed.\n"); } vlv2_plat_configure_clock(OSC_CAM1_CLK, flag); return 0; #elif defined(CONFIG_INTEL_SCU_IPC_UTIL) return intel_scu_ipc_osc_clk(OSC_CLK_CAM1, flag ? clock_khz : 0); #else pr_err("ov2685f clock is not set.\n"); return 0; #endif }
static int ov8865_flisclk_ctrl(struct v4l2_subdev *sd, int flag) { static const unsigned int clock_khz = 19200; OV8865_PLAT_LOG(1,"%s %d flag:%d\n", __func__, __LINE__, flag); ov8865_verify_gpio_power(); #ifdef CONFIG_VLV2_PLAT_CLK if (flag) { int ret; ret = vlv2_plat_set_clock_freq(OSC_CAM0_CLK, CLK_19P2MHz); if (ret) return ret; } usleep_range(2000, 2500); OV8865_PLAT_LOG(1,"%s %d VLV2 PLAT sleep 2ms for clock to stable\n", __func__, __LINE__); return vlv2_plat_configure_clock(OSC_CAM0_CLK, flag); #elif defined(CONFIG_INTEL_SCU_IPC_UTIL) return intel_scu_ipc_osc_clk(OSC_CLK_CAM0, flag ? clock_khz : 0); #else pr_err("ov8865 clock is not set.\n"); return 0; #endif }