unsigned int faItrigOutConfig(int id, unsigned short itrigDelay, unsigned short itrigWidth) { unsigned int retval=0; unsigned short s1, s2; if(id==0) id=fadcID[0]; if((id<=0) || (id>21) || (FAp[id] == NULL)) { logMsg("faItrigConfig: ERROR : FADC in slot %d is not initialized \n",id,0,0,0,0,0); return(0xffffffff); } if(itrigDelay>FA_ITRIG_MAX_DELAY) itrigDelay = FA_ITRIG_MAX_DELAY; if(itrigWidth>FA_ITRIG_MAX_WIDTH) itrigWidth = FA_ITRIG_MAX_WIDTH; FALOCK; if(itrigWidth) vmeWrite32(&(FAp[id]->hitsum_trig_width), itrigWidth); if(itrigDelay) vmeWrite32(&(FAp[id]->hitsum_trig_delay), itrigDelay); EIEIO; s1 = vmeRead32(&(FAp[id]->hitsum_trig_delay))&0xffff; s2 = vmeRead32(&(FAp[id]->hitsum_trig_width))&0xffff; retval = (s2<<16)|s1; FAUNLOCK; return(retval); }
void fadcFirmwareDownloadConfigData(int id) { unsigned int ArraySize; unsigned int ByteCount, ByteIndex, ByteNumber; unsigned int Word32Bits, SramAdr; unsigned int value; if(MSC_loaded != 1) { printf("%s: ERROR : Firmware was not loaded\n", __FUNCTION__); return; } /* ArraySize = sizeof(MSC_ARRAY); */ ArraySize = MSC_arraySize; ByteIndex = 0; SramAdr = 0; /* write SRAM address register */ /* start at 0 and increment address after write to mem1 data register */ FALOCK; vmeWrite32(&FAp[id]->mem_adr, 0x80000000); value = vmeRead32(&FAp[id]->mem_adr); FAUNLOCK; #ifdef DEBUG printf("%s: FADC %2d memory address at start of writes = 0x%08x\n\n", __FUNCTION__,id,value); #endif taskDelay(1); /* wait */ /* printf("Download Config Data... \n"); */ for (ByteCount = 0; ByteCount < ArraySize; ByteCount += 4) { Word32Bits = 0; for (ByteNumber = 0; ByteNumber < 4; ++ByteNumber) { Word32Bits = (MSC_ARRAY[ByteIndex] << (8 * ByteNumber)) | Word32Bits; ++ByteIndex; if(ByteIndex>MSC_MAX_SIZE) printf("**** TOO BIG! ****\n"); } /* write 32-bit data word to mem1 data register */ FALOCK; vmeWrite32(&FAp[id]->mem1_data, Word32Bits); FAUNLOCK; } #ifdef DEBUG FALOCK; value = vmeRead32(&FAp[id]->mem_adr); FAUNLOCK; printf("%s: FADC %2d memory address after write = 0x%08x\n\n", __FUNCTION__,id,value); #endif taskDelay(1); /* wait */ }
void titest1() { if(TIp==NULL) {printf("NULL\n");return;} printf("0x%08x(%d) 0x%08x(%d)\n", vmeRead32(&TIp->fiberLatencyMeasurement),vmeRead32(&TIp->fiberLatencyMeasurement), vmeRead32(&TIp->fiberAlignment),vmeRead32(&TIp->fiberAlignment)); }
int gtpVMEGetHostname(char **rval, int pFlag) { int slen=0, done=0; int i=0, ibyte=0; unsigned int read1, read2, hn[4]; char hostname[60], byte_c[2]; unsigned int shift=0, mask=0, byte=0; if(vGTPp==NULL) { printf("%s: ERROR: GTP not initialized\n",__FUNCTION__); return ERROR; } memset((char*)hostname,0,sizeof(hostname)); GTPLOCK; for(i=0; i<4; i++) { read1 = vmeRead32(&vGTPp->Hostname[2*i])&0xFFFF; read2 = vmeRead32(&vGTPp->Hostname[(2*i+1)])&0xFFFF; read1 = SSWAP(read1); read2 = SSWAP(read2); hn[i] = (read1) | (read2<<16); } GTPUNLOCK; strcpy(hostname,""); for(i=0; i<4; i++) { if(done) break; for(ibyte=0; ibyte<4; ibyte++) { shift = (ibyte*8); mask = (0xFF)<<shift; byte = (hn[i] & mask)>>shift; if(byte==0x0) { done=1; break; } sprintf(byte_c,"%c",byte); strcat(hostname,byte_c); } } if(pFlag) printf("%s: Hostname = >%s<\n", __FUNCTION__,hostname); strcpy((char *)rval,hostname); slen = (int)strlen(hostname); return slen; }
void faItrigPrintHBwidth(int id) { int ii; unsigned int wval[16]; if(id==0) id=fadcID[0]; if((id<=0) || (id>21) || (FAp[id] == NULL)) { printf("faItrigPrintHBwidth: ERROR : FADC in slot %d is not initialized \n",id); return; } FALOCK; vmeWrite32(&(FAp[id]->s_adr), FA_SADR_AUTO_INCREMENT); EIEIO; for(ii=0;ii<FA_MAX_ADC_CHANNELS;ii++) { wval[ii] = (vmeRead32(&(FAp[id]->hitsum_hit_width)) + 1)*FA_ADC_NS_PER_CLK; /* Get Values */ } FAUNLOCK; printf(" HitBit widths for FADC Inputs in slot %d:",id); for(ii=0;ii<FA_MAX_ADC_CHANNELS;ii++) { if((ii%4)==0) printf("\n"); printf("Chan %2d: %3d ns ",(ii+1),wval[ii]); } printf("\n"); }
unsigned int faItrigGetHBwidth(int id, unsigned int chan) { unsigned int rval; if(id==0) id=fadcID[0]; if((id<=0) || (id>21) || (FAp[id] == NULL)) { logMsg("faItrigGetHBwidth: ERROR : FADC in slot %d is not initialized \n",id,0,0,0,0,0); return(0xffffffff); } if(chan>15) { logMsg("faItrigGetHBwidth: ERROR : Channel # out of range (0-15)\n",0,0,0,0,0,0); return(0xffffffff); } FALOCK; vmeWrite32(&(FAp[id]->s_adr), chan); /* Set Channel */ EIEIO; rval = vmeRead32(&(FAp[id]->hitsum_hit_width)); /* Get Value */ FAUNLOCK; return(rval); }
unsigned int getVMEGetFirmwareVersion() { unsigned int rval=0; if(vGTPp==NULL) { printf("%s: ERROR: GTP not initialized\n",__FUNCTION__); return ERROR; } GTPLOCK; rval = (vmeRead32(&vGTPp->FirmwareRev[0]) & 0xFFFF) | (vmeRead32(&vGTPp->FirmwareRev[1]) & 0xFFFF)<<16; GTPUNLOCK; return rval; }
int fadcFirmwareTestReady(int id, int n_try, int pFlag) { int ii, value; int result; if(id==0) id=fadcID[0]; if((id<=0) || (id>21) || (FAp[id] == NULL)) { printf("%s: ERROR : ADC in slot %d is not initialized \n", __FUNCTION__,id); return ERROR; } result = ERROR; printf("%2d: ",id); fflush(stdout); for(ii = 0; ii < n_try; ii++) /* poll for ready bit */ { if((ii%180)==0) { printf("."); fflush(stdout); } taskDelay(1); /* wait */ FALOCK; value = vmeRead32(&FAp[id]->prom_reg1); FAUNLOCK; if( value & FA_PROMREG1_READY ) /* bit 31 asserted means ready */ { result = OK; break; } } printf(" Done\n"); if(pFlag) { if( ii == n_try ) /* failed to detect ready asserted */ printf("%s: FADC %2d NOT READY after %d wait cycles (1/60 sec)\n", __FUNCTION__,id,n_try); else printf("%s: FADC %2d READY after %d wait cycles (1/60 sec)\n", __FUNCTION__,id,(ii + 1)); } return result; }
/************************************************************ * * Setup Internal Trigger Table * 16 input channels can be latched to create a 16 bit * lookup address (0x0001 - 0xffff) in memory. The value 0 or 1 * at that memory address determines if a trigger pulse will be * generated (this is for Window or Table mode only) * * table = pointer to an array of 65536 values (1 or 0) that * will define a valid trigger or not. * (if = NULL, then the default table is loaded - all * input combinations will generate a trigger) */ int faItrigInitTable(int id, unsigned int *table) { int ii; unsigned int config; if(id==0) id=fadcID[0]; if((id<=0) || (id>21) || (FAp[id] == NULL)) { printf("faItrigSetMode: ERROR : FADC in slot %d is not initialized \n",id); return(ERROR); } FALOCK; /* Check and make sure we are not running */ config = vmeRead32(&(FAp[id]->hitsum_cfg)); if((config&FA_ITRIG_ENABLE_MASK) != FA_ITRIG_DISABLED) { printf("faItrigInitTable: ERROR: Cannot update Trigger Table while trigger is Enabled\n"); FAUNLOCK; return(ERROR); } if(table == NULL) { /* Use default Initialization - all combinations of inputs will be a valid trigger */ vmeWrite32(&(FAp[id]->s_adr), FA_SADR_AUTO_INCREMENT); vmeWrite32(&(FAp[id]->hitsum_pattern), 0); /* Make sure address 0 is not a valid trigger */ for(ii=1;ii<=0xffff;ii++) { vmeWrite32(&(FAp[id]->hitsum_pattern), 1); } }else{ /* Load specified table into hitsum FPGA */ vmeWrite32(&(FAp[id]->s_adr), FA_SADR_AUTO_INCREMENT); vmeWrite32(&(FAp[id]->hitsum_pattern), 0); /* Make sure address 0 is not a valid trigger */ for(ii=1;ii<=0xffff;ii++) { if(table[ii]) vmeWrite32(&(FAp[id]->hitsum_pattern), 1); else vmeWrite32(&(FAp[id]->hitsum_pattern), 0); } } FAUNLOCK; return(OK); }
int gtpVMEGetCpuStatus() { int rval=0; if(vGTPp==NULL) { printf("%s: ERROR: GTP not initialized\n",__FUNCTION__); return ERROR; } GTPLOCK; rval = vmeRead32(&vGTPp->CpuStatus[0]); rval = SSWAP(rval) & GTP_CPUSTATUS_BOOTED; GTPUNLOCK; return rval; }
unsigned int faItrigStatus(int id, int sFlag) { unsigned int status, config, tdelay, twidth, wMask, wWidth, cMask, sum_th; int vers, disabled, mode; if(id==0) id=fadcID[0]; if((id<=0) || (id>21) || (FAp[id] == NULL)) { printf("faItrigStatus: ERROR : FADC in slot %d is not initialized \n",id); return(ERROR); } /* Express Time in ns - 4ns/clk */ FALOCK; status = vmeRead32(&(FAp[id]->hitsum_status))&0xffff; config = vmeRead32(&(FAp[id]->hitsum_cfg))&0xffff; tdelay = (vmeRead32(&(FAp[id]->hitsum_trig_delay))&0xffff)*FA_ADC_NS_PER_CLK; twidth = (vmeRead32(&(FAp[id]->hitsum_trig_width))&0xffff)*FA_ADC_NS_PER_CLK; wMask = vmeRead32(&(FAp[id]->hitsum_window_bits))&0xffff; wWidth = (vmeRead32(&(FAp[id]->hitsum_window_width))&0xffff)*FA_ADC_NS_PER_CLK; cMask = vmeRead32(&(FAp[id]->hitsum_coin_bits))&0xffff; sum_th = vmeRead32(&(FAp[id]->hitsum_sum_thresh))&0xffff; FAUNLOCK; vers = status&FA_ITRIG_VERSION_MASK; mode = config&FA_ITRIG_MODE_MASK; disabled = config&FA_ITRIG_ENABLE_MASK; printf("\n FADC Internal Trigger (HITSUM) Configuration: \n"); if(disabled) printf(" Hitsum Status = 0x%04x Config = 0x%04x (mode = %d - Disabled)\n",status, config, mode); else printf(" Hitsum Status = 0x%04x Config = 0x%04x (mode = %d - Enabled)\n",status, config, mode); printf(" Trigger Out Delay = %6d ns Width = %5d ns\n", tdelay, twidth); printf(" Window Input Mask = 0x%04x Width = %5d ns\n", wMask, wWidth); printf(" Coin Input Mask = 0x%04x \n",cMask); printf(" Sum Mode Threshold = %d\n",sum_th); return(config); }
void faItrigDisable(int id) { unsigned int rval; if(id==0) id=fadcID[0]; if((id<=0) || (id>21) || (FAp[id] == NULL)) { logMsg("faItrigDisable: ERROR : FADC in slot %d is not initialized \n",id,0,0,0,0,0); return; } FALOCK; rval = vmeRead32(&(FAp[id]->hitsum_cfg)); rval |= FA_ITRIG_DISABLED; vmeWrite32(&(FAp[id]->hitsum_cfg), rval); FAUNLOCK; }
int faItrigGetTableVal (int id, unsigned short pMask) { unsigned int rval; if(id==0) id=fadcID[0]; if((id<=0) || (id>21) || (FAp[id] == NULL)) { logMsg("faItrigTableStatus: ERROR : FADC in slot %d is not initialized \n",id,0,0,0,0,0); return(ERROR); } FALOCK; vmeWrite32(&(FAp[id]->s_adr), pMask); EIEIO; /* Make sure write comes before read */ rval = vmeRead32(&(FAp[id]->hitsum_pattern)); FAUNLOCK; if(rval) return(1); else return(0); }
int faItrigSetHBwidth(int id, unsigned short hbWidth, unsigned short hbMask) { int ii; unsigned int config; if(id==0) id=fadcID[0]; if((id<=0) || (id>21) || (FAp[id] == NULL)) { printf("faItrigSetHBwidth: ERROR : FADC in slot %d is not initialized \n",id); return(ERROR); } /* Check and make sure we are not running */ FALOCK; config = vmeRead32(&(FAp[id]->hitsum_cfg)); if((config&FA_ITRIG_ENABLE_MASK) != FA_ITRIG_DISABLED) { printf("faItrigSetHBwidth: ERROR: Cannot set HB widths while trigger is Enabled\n"); FAUNLOCK; return(ERROR); } if(hbWidth==0) hbWidth = 1; /* Minimum Width allowed */ if(hbMask==0) hbMask = 0xffff; /* Set all Channels */ for(ii=0;ii<FA_MAX_ADC_CHANNELS;ii++) { if((1<<ii)&hbMask) { vmeWrite32(&(FAp[id]->s_adr), ii); /* Set Channel */ vmeWrite32(&(FAp[id]->hitsum_hit_width), hbWidth); /* Set Value */ } } FAUNLOCK; return(OK); }
int gtpVMEStatus(int pFlag) { struct GTPStruct st; int i=0, showregs=0; unsigned long gtpBase=0, tiBase=0; unsigned int version=0, hn[4]; if(vGTPp==NULL) { printf("%s: ERROR: GTP not initialized\n",__FUNCTION__); return ERROR; } if(pFlag & GTP_STATUS_SHOWREGS) showregs=1; tiBase = (unsigned long)TIp; gtpBase = (unsigned long)&(TIp->SWA[0]); GTPLOCK; for(i=0; i<2; i++) { st.BoardId[i] = vmeRead32(&vGTPp->BoardId[i]) & 0xFFFF; st.FirmwareRev[i] = vmeRead32(&vGTPp->FirmwareRev[i]) & 0xFFFF; st.CpuStatus[i] = vmeRead32(&vGTPp->CpuStatus[i]) & 0xFFFF; } for(i=0; i<8; i++) { st.Hostname[i] = vmeRead32(&vGTPp->Hostname[i]) & 0xFFFF; } GTPUNLOCK; version = ((st.BoardId[1] & 0xFFFF)<<16) | (st.BoardId[0] & 0xFFFF); for(i=0; i<4; i++) { hn[i] = (st.Hostname[2*i]) | ((st.Hostname[2*(i+1)])<<16); } /* Now printout what we've got */ printf("STATUS for GTP at TI (Local) base address 0x%08lx (0x%08lx) \n",gtpBase-tiBase,gtpBase); printf("--------------------------------------------------------------------------------\n"); printf(" Type = %d Firmware Version %d.%d\n", (version & GTP_FIRMWAREREV_TYPE_MASK)>>16, (version & GTP_FIRMWAREREV_MAJOR_MASK)>>8, (version & GTP_FIRMWAREREV_MINOR_MASK)); if(showregs) { printf(" Raw Registers\n"); printf(" BoardId[0] (0x%04x) = 0x%04x\t", (unsigned int)(&vGTPp->BoardId[0] - gtpBase), st.BoardId[0]); printf(" BoardId[1] (0x%04x) = 0x%04x\n", (unsigned int)(&vGTPp->BoardId[1] - gtpBase), st.BoardId[1]); printf(" FirmwareRev[0] (0x%04x) = 0x%04x\t", (unsigned int)(&vGTPp->FirmwareRev[0] - gtpBase), st.FirmwareRev[0]); printf(" FirmwareRev[1] (0x%04x) = 0x%04x\n", (unsigned int)(&vGTPp->FirmwareRev[1] - gtpBase), st.FirmwareRev[1]); printf(" CpuStatus[0] (0x%04x) = 0x%04x\t", (unsigned int)(&vGTPp->CpuStatus[0] - gtpBase), st.CpuStatus[0]); printf(" CpuStatus[1] (0x%04x) = 0x%04x\n", (unsigned int)(&vGTPp->CpuStatus[1] - gtpBase), st.CpuStatus[1]); for(i=0; i<8; i=i+2) { printf(" Hostname[%d] (0x%04x) = 0x%04x\t", i, (unsigned int)(&vGTPp->Hostname[i] - gtpBase), st.Hostname[i]); printf(" Hostname[%d] (0x%04x) = 0x%04x\n", i+1, (unsigned int)(&vGTPp->Hostname[i+1] - gtpBase), st.Hostname[i+1]); } for(i=0; i<4; i=i+2) { printf(" hn[%d] = 0x%08x\t", i,hn[i]); printf(" hn[%d] = 0x%08x\n", i+1,hn[i+1]); } } return OK; }
int fadcFirmwareZeroSRAM (int id) { int ii, value=0, value_1=0, value_2=0; int ErrorCount=0, stopPrint=0; if(id==0) id=fadcID[0]; if((id<=0) || (id>21) || (FAp[id] == NULL)) { printf("%s: ERROR : ADC in slot %d is not initialized \n", __FUNCTION__,id); return ERROR; } /* set address = 0; allow increment on mem2 access */ FALOCK; vmeWrite32(&FAp[id]->mem_adr, 0x0000 | FA_MEM_ADR_INCR_MEM2); for( ii = 0; ii < 0x80000; ii++) /* write ZERO to entire memory */ { vmeWrite32(&FAp[id]->mem1_data, 0); vmeWrite32(&FAp[id]->mem2_data, 0); } /* reset address = 0; allow increment on mem2 access */ vmeWrite32(&FAp[id]->mem_adr, 0x0000 | FA_MEM_ADR_INCR_MEM2); FAUNLOCK; /* read and test expected memory data */ for( ii = 0; ii < 0x80000; ii++) { FALOCK; value_1 = vmeRead32(&FAp[id]->mem1_data); value_2 = vmeRead32(&FAp[id]->mem2_data); FAUNLOCK; if( (value_1 != 0) || (value_2 != 0) ) { ErrorCount++; FALOCK; value = vmeRead32(&FAp[id]->mem_adr) & 0xFFFFF; FAUNLOCK; if(!stopPrint) { printf("%s: ERROR: FADC %2d address = %8X mem1 read = %8X mem2 read = %8X\n", __FUNCTION__,id, value, value_1, value_2); taskDelay(1); /* wait */ } if(ErrorCount==80) { printf("%s: Further errors for FADC %2d will not be displayed\n", __FUNCTION__,id); stopPrint=1; } } } if(ErrorCount) return ERROR; return OK; }
int fadcFirmwareVerifyDownload (int id) { unsigned int ArraySize; unsigned int ByteCount, ByteIndex, ByteNumber; unsigned int ExpWord32Bits, SramAdr, RdWord32Bits; int ErrorCount=0, stopPrint=0; int value; if(id==0) id=fadcID[0]; if((id<=0) || (id>21) || (FAp[id] == NULL)) { printf("%s: ERROR : ADC in slot %d is not initialized \n", __FUNCTION__,id); return ERROR; } if(MSC_loaded != 1) { printf("%s: ERROR : Firmware was not loaded\n", __FUNCTION__); return ERROR; } /* ArraySize = sizeof(MSC_ARRAY); */ ArraySize = MSC_arraySize; ByteIndex = 0; SramAdr = 0; /* write SRAM address register */ /* start at 0 and increment address after read from mem1 data register */ FALOCK; vmeWrite32(&FAp[id]->mem_adr, 0x0000 | FA_MEM_ADR_INCR_MEM1); value = vmeRead32(&FAp[id]->mem_adr); FAUNLOCK; #ifdef DEBUG printf("%s: FADC %2d memory address at start of read = 0x%08x\n\n", __FUNCTION__,id,value); #endif taskDelay(2); /* wait */ for (ByteCount = 0; ByteCount < ArraySize; ByteCount += 4) { /* get expected value */ ExpWord32Bits = 0; for (ByteNumber = 0; ByteNumber < 4; ++ByteNumber) { ExpWord32Bits = (MSC_ARRAY[ByteIndex] << (8 * ByteNumber)) | ExpWord32Bits; ++ByteIndex; } /* read 32-bit data word from mem1 data register */ FALOCK; RdWord32Bits = (unsigned int)vmeRead32(&FAp[id]->mem1_data); FAUNLOCK; #ifdef DEBUG if(ByteCount<40) printf("RdWord32Bits = 0x%08x\n",RdWord32Bits); #endif /* test if read value = expected value */ if (RdWord32Bits != ExpWord32Bits) { ErrorCount++; if(!stopPrint) printf("%s: ERROR: FADC %2d ByteCount %8d Expect %08X Read %08X\n", __FUNCTION__,id, ByteCount, ExpWord32Bits, RdWord32Bits); if( ErrorCount==80 ) { printf("%s: Further errors for FADC %2d will not be displayed\n", __FUNCTION__,id); /* getchar(); */ stopPrint=1; } /* if( ErrorCount>1000 ) */ /* stopPrint=1; */ } } FALOCK; value = vmeRead32(&FAp[id]->mem_adr); FAUNLOCK; #ifdef DEBUG printf("%s: memory address after read = 0x%08x\n\n", __FUNCTION__,value); #endif if(ErrorCount) printf("%s: ErrorCount = %d\n",__FUNCTION__,ErrorCount); taskDelay(1); /* wait */ if(ErrorCount) return ERROR; return OK; }
/* gtpInit - Initialize the Global Trigger Processor module */ int gtpVMEInit(int rFlag) { unsigned long tiBase=0, gtpBase=0; unsigned int tmp1, tmp2, BoardId=0, version=0; if(TIp==NULL) { printf("%s: ERROR: TI not initialized\n",__FUNCTION__); return ERROR; } /* Verify that the ctp registers are in the correct space for the TI I2C */ tiBase = (unsigned long)TIp; gtpBase = (unsigned long)&(TIp->SWA[0]); if( (gtpBase-tiBase) != GTPBASE) { printf("%s: ERROR: GTP memory structure not in correct VME Space!\n", __FUNCTION__); printf(" current base = 0x%lx expected base = 0x%lx\n", gtpBase-tiBase, (unsigned long)GTPBASE); return ERROR; } vGTPp = (struct GTPStruct *)(&TIp->SWA[0]); /* Check the module ID, to confirm we've got a GTP in there */ GTPLOCK; tmp1 = vmeRead32(&vGTPp->BoardId[1])&0xFFFF; tmp2 = vmeRead32(&vGTPp->BoardId[0])&0xFFFF; BoardId = SSWAP(tmp1)<<16|SSWAP(tmp2); tmp1 = vmeRead32(&vGTPp->FirmwareRev[1])&0xFFFF; tmp2 = vmeRead32(&vGTPp->FirmwareRev[0])&0xFFFF; version = SSWAP(tmp1)<<16|SSWAP(tmp2); GTPUNLOCK; if(BoardId != (GTP_BOARDID)) { printf("%s: ERROR: Invalid GTP Board ID (0x%08x)\n", __FUNCTION__,BoardId); return ERROR; } if(version == 0xffffffff) { printf("%s: ERROR: Unable to read GTP version (returned 0x%x)\n", __FUNCTION__,version); return ERROR; } printf("%s: GTP (Type %d v%d.%d) initialized at Local Base address 0x%lx\n", __FUNCTION__, (version & GTP_FIRMWAREREV_TYPE_MASK)>>16, (version & GTP_FIRMWAREREV_MAJOR_MASK)>>8, (version & GTP_FIRMWAREREV_MINOR_MASK), gtpBase); return OK; }
/************************************************************ * * Setup Internal Triggering * * Four Modes of Operation (tmode) * 1) Table Mode * 2) Window Mode * 3) Coincidence Mode * 4) Sum Mode * * wMask = Mask of 16 channels to be enabled for Window Mode * wWidth = Width of trigger window before latching (in clocks) * cMask = Mask of 16 channels to be enabled for Coincidence Mode * sumThresh = 10-12 bit threshold for Sum trigger to be latched * tTable = pointer to trigger table (65536 values) to be loaded */ int faItrigSetMode(int id, int tmode, unsigned int wMask, unsigned int wWidth, unsigned int cMask, unsigned int sumThresh, unsigned int *tTable) { int ii; unsigned int config, stat, wTime; if(id==0) id=fadcID[0]; if((id<=0) || (id>21) || (FAp[id] == NULL)) { printf("faItrigSetMode: ERROR : FADC in slot %d is not initialized \n",id); return(ERROR); } /* Make sure we are not enabled or running */ FALOCK; config = vmeRead32(&(FAp[id]->hitsum_cfg))&FA_ITRIG_CONFIG_MASK; if((config&FA_ITRIG_ENABLE_MASK) == 0) { printf("faItrigSetMode: ERROR: Internal triggers are enabled - Disable first\n"); FAUNLOCK; return(ERROR); } if((tmode<1)||(tmode>4)) { printf("faItrigSetMode: ERROR: Trigger mode (%d) out of range (tmode = 1-4)\n",tmode); FAUNLOCK; return(ERROR); } /* Check if we need to load a trigger table */ if(tTable != NULL) { printf("faItrigSetMode: Loading trigger table from address 0x%08x \n",(unsigned int) tTable); vmeWrite32(&(FAp[id]->s_adr), FA_SADR_AUTO_INCREMENT); vmeWrite32(&(FAp[id]->hitsum_pattern), 0); /* Make sure address 0 is not a valid trigger */ for(ii=1;ii<=0xffff;ii++) { if(tTable[ii]) vmeWrite32(&(FAp[id]->hitsum_pattern), 1); else vmeWrite32(&(FAp[id]->hitsum_pattern), 0); } } switch(tmode) { case FA_ITRIG_SUM_MODE: /* Load Sum Threshhold if in range */ if((sumThresh > 0)&&(sumThresh <= 0xffff)) { vmeWrite32(&(FAp[id]->hitsum_sum_thresh), sumThresh); }else{ printf("faItrigSetMode: ERROR: Sum Threshold out of range (0<st<=0xffff)\n"); FAUNLOCK; return(ERROR); } stat = (config&~FA_ITRIG_MODE_MASK) | FA_ITRIG_SUM_MODE; vmeWrite32(&(FAp[id]->hitsum_cfg), stat); printf("faItrigSetMode: Configure for SUM Mode (Threshold = 0x%x)\n",sumThresh); break; case FA_ITRIG_COIN_MODE: /* Set Coincidence Input Channels */ if((cMask > 0)&&(cMask <= 0xffff)) { vmeWrite32(&(FAp[id]->hitsum_coin_bits), cMask); }else{ printf("faItrigSetMode: ERROR: Coincidence channel mask out of range (0<cc<=0xffff)\n"); FAUNLOCK; return(ERROR); } stat = (config&~FA_ITRIG_MODE_MASK) | FA_ITRIG_COIN_MODE; vmeWrite32(&(FAp[id]->hitsum_cfg), stat); printf("faItrigSetMode: Configure for COINCIDENCE Mode (channel mask = 0x%x)\n",cMask); break; case FA_ITRIG_WINDOW_MODE: /* Set Trigger Window width and channel mask */ if((wMask > 0)&&(wMask <= 0xffff)) { vmeWrite32(&(FAp[id]->hitsum_window_bits), wMask); }else{ printf("faItrigSetMode: ERROR: Trigger Window channel mask out of range (0<wc<=0xffff)\n"); FAUNLOCK; return(ERROR); } if((wWidth > 0)&&(wWidth <= FA_ITRIG_WINDOW_MAX_WIDTH)) { vmeWrite32(&(FAp[id]->hitsum_window_width), wWidth); wTime = 4*wWidth; }else{ printf("faItrigSetMode: ERROR: Trigger Window width out of range (0<ww<=0x200)\n"); FAUNLOCK; return(ERROR); } stat = (config&~FA_ITRIG_MODE_MASK) | FA_ITRIG_WINDOW_MODE; vmeWrite32(&(FAp[id]->hitsum_cfg), stat); printf("faItrigSetMode: Configure for Trigger WINDOW Mode (channel mask = 0x%x, width = %d ns)\n", cMask,wTime); break; case FA_ITRIG_TABLE_MODE: stat = (config&~FA_ITRIG_MODE_MASK) | FA_ITRIG_TABLE_MODE; vmeWrite32(&(FAp[id]->hitsum_cfg), stat); printf("faItrigSetMode: Configure for Trigger TABLE Mode\n"); } FAUNLOCK; return(OK); }