asmlinkage void vrc5477_irq_dispatch(struct pt_regs *regs) { extern unsigned int do_IRQ(int irq, struct pt_regs *regs); u32 intStatus; u32 bitmask; u32 i; db_assert(ddb_in32(DDB_INT2STAT) == 0); db_assert(ddb_in32(DDB_INT3STAT) == 0); db_assert(ddb_in32(DDB_INT4STAT) == 0); db_assert(ddb_in32(DDB_NMISTAT) == 0); if (ddb_in32(DDB_INT1STAT) != 0) { #if defined(CONFIG_DEBUG) vrc5477_show_int_regs(); #endif panic("error interrupt has happened."); } intStatus = ddb_in32(DDB_INT0STAT); for (i=0, bitmask=1; i<= NUM_5477_IRQS; bitmask <<=1, i++) { /* do we need to "and" with the int mask? */ if (intStatus & bitmask) { do_IRQ(8 + i, regs); } } }
static void vrc5477_irq_dispatch(struct pt_regs *regs) { u32 intStatus; u32 bitmask; u32 i; db_assert(ddb_in32(DDB_INT2STAT) == 0); db_assert(ddb_in32(DDB_INT3STAT) == 0); db_assert(ddb_in32(DDB_INT4STAT) == 0); db_assert(ddb_in32(DDB_NMISTAT) == 0); if (ddb_in32(DDB_INT1STAT) != 0) { #if defined(CONFIG_RUNTIME_DEBUG) vrc5477_show_int_regs(); #endif panic("error interrupt has happened."); } intStatus = ddb_in32(DDB_INT0STAT); if (mips_machtype == MACH_NEC_ROCKHOPPERII) { /* check for i8259 interrupts */ if (intStatus & (1 << VRC5477_I8259_CASCADE)) { int i8259_irq = i8259_interrupt_ack(); do_IRQ(I8259_IRQ_BASE + i8259_irq, regs); return; } } for (i=0, bitmask=1; i<= NUM_5477_IRQS; bitmask <<=1, i++) { /* do we need to "and" with the int mask? */ if (intStatus & bitmask) { do_IRQ(VRC5477_IRQ_BASE + i, regs); return; } } }