/* * serial port input * tmo timeout (milliseconds) * You can not wait forever. * return value >= 0 : character code * -1 : timeout * input data using buffer. * receive error is ignored. */ LOCAL W getSIO_16550(SIOCB *scb, W tmo ) { W sts, c = 0; RSDRV_PWON(); tmo *= 1000/20; /* convert tmo to 20 usec units */ /* receive as much data as possible in the receive buffer */ while (scb->iptr - scb->optr < SIO_RCVBUFSZ) { /* is there data in FIFO? */ if ( !((sts = IN(regLSTS)) & (LS_DRDY | LS_RxERR))) { if (scb->iptr != scb->optr) break; /* already received */ if (tmo-- <= 0) break; /* timeout */ waitUsec(20); continue; } /* receive data input */ if (sts & LS_DRDY) c = IN(regDATA); /* error check */ if (sts & LS_RxERR) continue; /* set data to rcvbuf */ scb->rcvbuf[scb->iptr++ & SIO_PTRMSK] = c; } /* return the data in rcvbuf */ return (scb->iptr == scb->optr)? -1 : scb->rcvbuf[scb->optr++ & SIO_PTRMSK]; }
/* wait for data of SPI for PMIC communication */ LOCAL void pmicWait(void) { W i; for (i = 1000000; i > 0; i--) { if (in_w(SPn_RAW_STATUS(SP0)) & 0x0004) break; waitUsec(1); } if (!i) pmicInit(); return; }
/* initialize SPI for PMIC communication */ LOCAL void pmicInit(void) { out_w(SPn_MODE(SP0), 0x2700); /* 8bit, CS0, Master, CPU mode */ out_w(SPn_TIECS(SP0), 0x000f); /* CS0: follow the specification by SPn_POL */ out_w(SPn_POL(SP0), SPIPol); out_w(SPn_ENCLR(SP0), ~0); /* interrupt disable */ out_w(SPn_CONTROL(SP0), 0x0100); /* start reset */ waitUsec(10); out_w(SPn_CONTROL(SP0), 0x0000); /* release reset */ out_w(SPn_CONTROL2(SP0), 0x0000); return; }
// // loadSR void LiquidCrystal_SR2W::loadSR(uint8_t val) { // Clear to keep Enable LOW while clocking in new bits fio_shiftOut(_srDataRegister, _srDataMask, _srClockRegister, _srClockMask); // clock out SR data byte fio_shiftOut(_srDataRegister, _srDataMask, _srClockRegister, _srClockMask, val, MSBFIRST); // strobe LCD enable which can now be toggled by the data line ATOMIC_BLOCK(ATOMIC_RESTORESTATE) { fio_digitalWrite_HIGH(_srDataRegister, _srDataMask); waitUsec (1); // enable pulse must be >450ns fio_digitalWrite_SWITCHTO(_srDataRegister, _srDataMask, LOW); } // end critical section }