void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { static const u16 spd_addr[] = { DIMM0, DIMM2, 0, 0, /* Channel A (DIMM_A1, DIMM_A2) */ DIMM1, DIMM3, 0, 0, /* Channel B (DIMM_B1, DIMM_B2) */ }; struct sys_info *sysinfo = &sysinfo_car; int needs_reset = 0; unsigned bsp_apicid = 0; if (!cpu_init_detectedx && boot_cpu()) { /* Allow the HT devices to be found. */ enumerate_ht_chain(); sio_setup(); } if (bist == 0) bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); ite_conf_clkin(CLKIN_DEV, ITE_UART_CLK_PREDIVIDE_24); ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); setup_mb_resource_map(); report_bist_failure(bist); console_init(); printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo, sysinfo + 1); printk(BIOS_DEBUG, "bsp_apicid=0x%02x\n", bsp_apicid); /* In BSP so could hold all AP until sysinfo is in RAM. */ set_sysinfo_in_ram(0); setup_coherent_ht_domain(); /* Routing table and start other core0. */ wait_all_core0_started(); #if CONFIG_LOGICAL_CPUS /* * It is said that we should start core1 after all core0 launched * becase optimize_link_coherent_ht is moved out from * setup_coherent_ht_domain, so here need to make sure last core0 is * started, esp for two way system (there may be APIC ID conflicts in * that case). */ start_other_cores(); wait_all_other_cores_started(bsp_apicid); #endif /* Set up chains and store link pair for optimization later. */ ht_setup_chains_x(sysinfo); /* Init sblnk and sbbusn, nodes, sbdn. */ /* TODO: FIDVID */ init_timer(); /* Need to use TMICT to synchronize FID/VID. */ needs_reset |= optimize_link_coherent_ht(); needs_reset |= optimize_link_incoherent_ht(sysinfo); needs_reset |= mcp55_early_setup_x(); /* * FIDVID change will issue one LDTSTOP and the HT change will be * effective too. */ if (needs_reset) { printk(BIOS_INFO, "ht reset -\n"); soft_reset(); } allow_all_aps_stop(bsp_apicid); fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr); enable_smbus(); sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo); /* BSP switch stack to RAM and copy sysinfo RAM now. */ post_cache_as_ram(); }
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { struct sys_info *sysinfo = &sysinfo_car; static const u8 spd_addr[] = {RC00, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, }; u32 bsp_apicid = 0, val; msr_t msr; if (!cpu_init_detectedx && boot_cpu()) { /* Nothing special needs to be done to find bus 0 */ /* Allow the HT devices to be found */ /* mov bsp to bus 0xff when > 8 nodes */ set_bsp_node_CHtExtNodeCfgEn(); enumerate_ht_chain(); //enable port80 decoding and southbridge poweron init sb_Poweron_Init(); } post_code(0x30); if (bist == 0) { bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); /* mmconf is inited in init_cpus */ /* All cores run this but the BSP(node0,core0) is the only core that returns. */ } post_code(0x32); enable_rs780_dev8(); sb800_clk_output_48Mhz(); w83627hf_set_clksel_48(PNP_DEV(CONFIG_SIO_PORT, 0)); w83627hf_enable_serial(0, CONFIG_TTYS0_BASE); uart_init(); console_init(); printk(BIOS_DEBUG, "\n"); // dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x200, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE); /* Halt if there was a built in self test failure */ report_bist_failure(bist); // Load MPB val = cpuid_eax(1); printk(BIOS_DEBUG, "BSP Family_Model: %08x \n", val); printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1); printk(BIOS_DEBUG, "bsp_apicid = %02x \n", bsp_apicid); printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx \n", cpu_init_detectedx); /* Setup sysinfo defaults */ set_sysinfo_in_ram(0); #if CONFIG_UPDATE_CPU_MICROCODE update_microcode(val); #endif post_code(0x33); cpuSetAMDMSR(); post_code(0x34); amd_ht_init(sysinfo); post_code(0x35); /* Setup nodes PCI space and start core 0 AP init. */ finalize_node_setup(sysinfo); /* Setup any mainboard PCI settings etc. */ setup_mb_resource_map(); post_code(0x36); /* wait for all the APs core0 started by finalize_node_setup. */ /* FIXME: A bunch of cores are going to start output to serial at once. It would be nice to fixup prink spinlocks for ROM XIP mode. I think it could be done by putting the spinlock flag in the cache of the BSP located right after sysinfo. */ wait_all_core0_started(); #if CONFIG_LOGICAL_CPUS /* Core0 on each node is configured. Now setup any additional cores. */ printk(BIOS_DEBUG, "start_other_cores()\n"); start_other_cores(); post_code(0x37); wait_all_other_cores_started(bsp_apicid); #endif post_code(0x38); /* run _early_setup before soft-reset. */ rs780_early_setup(); #if CONFIG_SET_FIDVID msr = rdmsr(0xc0010071); printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo); post_code(0x39); if (!warm_reset_detect(0)) { // BSP is node 0 init_fidvid_bsp(bsp_apicid, sysinfo->nodes); } else { init_fidvid_stage2(bsp_apicid, 0); // BSP is node 0 } post_code(0x3A); /* show final fid and vid */ msr=rdmsr(0xc0010071); printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo); #endif rs780_htinit(); /* Reset for HT, FIDVID, PLL and errata changes to take affect. */ if (!warm_reset_detect(0)) { print_info("...WARM RESET...\n\n\n"); soft_reset(); die("After soft_reset_x - shouldn't see this message!!!\n"); } post_code(0x3B); /* It's the time to set ctrl in sysinfo now; */ printk(BIOS_DEBUG, "fill_mem_ctrl()\n"); fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr); post_code(0x40); // die("Die Before MCT init."); printk(BIOS_DEBUG, "raminit_amdmct()\n"); raminit_amdmct(sysinfo); post_code(0x41); /* dump_pci_device_range(PCI_DEV(0, 0x18, 0), 0, 0x200); dump_pci_device_range(PCI_DEV(0, 0x18, 1), 0, 0x200); dump_pci_device_range(PCI_DEV(0, 0x18, 2), 0, 0x200); dump_pci_device_range(PCI_DEV(0, 0x18, 3), 0, 0x200); */ // ram_check(0x00200000, 0x00200000 + (640 * 1024)); // ram_check(0x40200000, 0x40200000 + (640 * 1024)); // die("After MCT init before CAR disabled."); rs780_before_pci_init(); post_code(0x42); post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB. post_code(0x43); // Should never see this post code. }
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); u32 bsp_apicid = 0, val; msr_t msr; if (!cpu_init_detectedx && boot_cpu()) { /* Nothing special needs to be done to find bus 0 */ /* Allow the HT devices to be found */ /* mov bsp to bus 0xff when > 8 nodes */ set_bsp_node_CHtExtNodeCfgEn(); enumerate_ht_chain(); bcm5785_enable_lpc(); pc87417_enable_dev(RTC_DEV); /* Enable RTC */ } post_code(0x30); if (bist == 0) bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); pilot_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); /* Halt if there was a built in self test failure */ report_bist_failure(bist); pilot_early_init(SERIAL_DEV); //config port is being taken from SERIAL_DEV val = cpuid_eax(1); printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1); printk(BIOS_DEBUG, "bsp_apicid = %02x\n", bsp_apicid); printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); /* Setup sysinfo defaults */ set_sysinfo_in_ram(0); #if CONFIG_UPDATE_CPU_MICROCODE update_microcode(val); #endif post_code(0x33); cpuSetAMDMSR(); post_code(0x34); amd_ht_init(sysinfo); post_code(0x35); /* Setup nodes PCI space and start core 0 AP init. */ finalize_node_setup(sysinfo); post_code(0x36); /* wait for all the APs core0 started by finalize_node_setup. */ /* FIXME: A bunch of cores are going to start output to serial at once. * It would be nice to fixup prink spinlocks for ROM XIP mode. * I think it could be done by putting the spinlock flag in the cache * of the BSP located right after sysinfo. */ wait_all_core0_started(); #if CONFIG_LOGICAL_CPUS==1 /* Core0 on each node is configured. Now setup any additional cores. */ printk(BIOS_DEBUG, "start_other_cores()\n"); start_other_cores(); post_code(0x37); wait_all_other_cores_started(bsp_apicid); #endif #if CONFIG_SET_FIDVID msr = rdmsr(0xc0010071); printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); /* FIXME: The sb fid change may survive the warm reset and only * need to be done once.*/ enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn); post_code(0x39); if (!warm_reset_detect(0)) { // BSP is node 0 init_fidvid_bsp(bsp_apicid, sysinfo->nodes); } else { init_fidvid_stage2(bsp_apicid, 0); // BSP is node 0 } post_code(0x3A); /* show final fid and vid */ msr=rdmsr(0xc0010071); printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); #endif init_timer(); /* Reset for HT, FIDVID, PLL and errata changes to take affect. */ if (!warm_reset_detect(0)) { print_info("...WARM RESET...\n\n\n"); soft_reset(); die("After soft_reset_x - shouldn't see this message!!!\n"); } /* It's the time to set ctrl in sysinfo now; */ fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr); enable_smbus(); //do we need apci timer, tsc...., only debug need it for better output /* all ap stopped? */ // init_timer(); // Need to use TMICT to synconize FID/VID printk(BIOS_DEBUG, "raminit_amdmct()\n"); raminit_amdmct(sysinfo); post_code(0x41); bcm5785_early_setup(); post_cache_as_ram(); }
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { static const uint16_t spd_addr[] = { // Node 0 DIMM0, DIMM1, DIMM2, 0, 0, 0, 0, 0, // Node 1 0, 0, 0, 0, 0, 0, 0, 0, }; unsigned bsp_apicid = 0; int needs_reset = 0; struct sys_info *sysinfo = &sysinfo_car; sio_init(); w83697hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); enable_rom_decode(); print_info("now booting... fallback\n"); /* Is this a CPU only reset? Or is this a secondary CPU? */ if (!cpu_init_detectedx && boot_cpu()) { /* Nothing special needs to be done to find bus 0. */ /* Allow the HT devices to be found. */ enumerate_ht_chain(); } // FIXME why is this executed again? ---> sio_init(); w83697hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); enable_rom_decode(); // <--- FIXME why is this executed again? print_info("now booting... real_main\n"); if (bist == 0) bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); /* Halt if there was a built in self test failure. */ report_bist_failure(bist); setup_default_resource_map(); setup_coherent_ht_domain(); wait_all_core0_started(); print_info("now booting... Core0 started\n"); #if CONFIG_LOGICAL_CPUS /* It is said that we should start core1 after all core0 launched. */ start_other_cores(); wait_all_other_cores_started(bsp_apicid); #endif init_timer(); ht_setup_chains_x(sysinfo); /* Init sblnk and sbbusn, nodes, sbdn. */ needs_reset = optimize_link_coherent_ht(); needs_reset |= optimize_link_incoherent_ht(sysinfo); needs_reset |= k8t890_early_setup_ht(); if (needs_reset) { print_debug("ht reset -\n"); soft_reset(); } /* the HT settings needs to be OK, because link freq change may cause HT disconnect */ vt8237_sb_enable_fid_vid(); enable_fid_change(); init_fidvid_bsp(bsp_apicid); /* Stop the APs so we can start them later in init. */ allow_all_aps_stop(bsp_apicid); /* It's the time to set ctrl now. */ fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr); enable_smbus(); /* this seems to be some GPIO on the SMBus--in any case, setting these * two bits reduces the pullup impedance of the bus lines and is required * in order to be able to read SPD info */ smbus_write_byte(0x48, 0x07, smbus_read_byte(0x48, 0x07) | 0x80); smbus_write_byte(0x4a, 0x07, smbus_read_byte(0x4a, 0x07) | 0x10); unsigned char mask; mask = 0; // mask |= 1 /* AGP voltage 1.7 V (not verified, just vendor BIOS value) */ // mask |= 2 /* V-Link voltage 2.6 V (not verified either) */ smbus_write_byte(0x4a, 0x00, (smbus_read_byte(0x4a, 0x00) & ~0x0f) | (0x0f ^ (mask << 2))); smbus_write_byte(0x4a, 0x01, (smbus_read_byte(0x4a, 0x01) & ~0x03) | (0x03 ^ mask)); mask = 25; /* RAM voltage in decivolts, valid range from 25 to 28 */ mask = 3 - (mask - 25); smbus_write_byte(0x4a, 0x02, 0x4f | (mask << 4)); smbus_write_byte(0x4a, 0x03, 0x04 | mask); sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo); post_cache_as_ram(); }
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { static const uint16_t spd_addr [] = { // Node 0 (0xa<<3)|0, (0xa<<3)|2, 0, 0, (0xa<<3)|1, (0xa<<3)|3, 0, 0, // Node 1 (0xa<<3)|4, (0xa<<3)|6, 0, 0, (0xa<<3)|5, (0xa<<3)|7, 0, 0, }; int needs_reset; unsigned bsp_apicid = 0; struct mem_controller ctrl[8]; unsigned nodes; if (!cpu_init_detectedx && boot_cpu()) { /* Nothing special needs to be done to find bus 0 */ /* Allow the HT devices to be found */ enumerate_ht_chain(); sio_setup(); /* Setup the ck804 */ ck804_enable_rom(); } if (bist == 0) { bsp_apicid = init_cpus(cpu_init_detectedx); } lpc47b397_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); console_init(); /* Halt if there was a built in self test failure */ report_bist_failure(bist); setup_ultra40_resource_map(); needs_reset = setup_coherent_ht_domain(); wait_all_core0_started(); #if CONFIG_LOGICAL_CPUS==1 // It is said that we should start core1 after all core0 launched start_other_cores(); wait_all_other_cores_started(bsp_apicid); #endif needs_reset |= ht_setup_chains_x(); needs_reset |= ck804_early_setup_x(); if (needs_reset) { print_info("ht reset -\n"); soft_reset(); } allow_all_aps_stop(bsp_apicid); nodes = get_nodes(); //It's the time to set ctrl now; fill_mem_ctrl(nodes, ctrl, spd_addr); enable_smbus(); sdram_initialize(nodes, ctrl); post_cache_as_ram(); }
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { static const uint16_t spd_addr[] = { // Node 0 DIMM0, DIMM2, 0, 0, 0, 0, 0, 0, // Node 1 DIMM1, DIMM3, 0, 0, 0, 0, 0, 0, }; unsigned bsp_apicid = 0; int needs_reset = 0; struct sys_info *sysinfo = &sysinfo_car; sio_init(); winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); enable_rom_decode(); printk(BIOS_INFO, "now booting... fallback\n"); /* Is this a CPU only reset? Or is this a secondary CPU? */ if (!cpu_init_detectedx && boot_cpu()) { /* Nothing special needs to be done to find bus 0. */ /* Allow the HT devices to be found. */ enumerate_ht_chain(); } printk(BIOS_INFO, "now booting... real_main\n"); if (bist == 0) bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); /* Halt if there was a built in self test failure. */ report_bist_failure(bist); setup_default_resource_map(); setup_coherent_ht_domain(); wait_all_core0_started(); printk(BIOS_INFO, "now booting... Core0 started\n"); #if CONFIG_LOGICAL_CPUS /* It is said that we should start core1 after all core0 launched. */ start_other_cores(); wait_all_other_cores_started(bsp_apicid); #endif init_timer(); ht_setup_chains_x(sysinfo); /* Init sblnk and sbbusn, nodes, sbdn. */ needs_reset = optimize_link_coherent_ht(); needs_reset |= optimize_link_incoherent_ht(sysinfo); needs_reset |= k8t890_early_setup_ht(); if (needs_reset) { printk(BIOS_DEBUG, "ht reset -\n"); soft_reset(); } /* the HT settings needs to be OK, because link freq chnage may cause HT disconnect */ enable_fid_change(); init_fidvid_bsp(bsp_apicid); /* Stop the APs so we can start them later in init. */ allow_all_aps_stop(bsp_apicid); /* It's the time to set ctrl now. */ fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr); enable_smbus(); sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo); post_cache_as_ram(); }
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { static const uint16_t spd_addr[] = { // first node DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, // second node DIMM4, DIMM6, 0, 0, DIMM5, DIMM7, 0, 0, }; struct sys_info *sysinfo = &sysinfo_car; int needs_reset; unsigned bsp_apicid = 0; if (!cpu_init_detectedx && boot_cpu()) { /* Nothing special needs to be done to find bus 0 */ /* Allow the HT devices to be found */ enumerate_ht_chain(); bcm5785_enable_lpc(); pc87417_enable_dev(RTC_DEV); /* Enable RTC */ } if (bist == 0) bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); pilot_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); /* Halt if there was a built in self test failure */ report_bist_failure(bist); // setup_early_ipmi_serial(); pilot_early_init(SERIAL_DEV); //config port is being taken from SERIAL_DEV printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1); printk(BIOS_DEBUG, "bsp_apicid=%02x\n", bsp_apicid); set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram setup_coherent_ht_domain(); wait_all_core0_started(); #if CONFIG_LOGICAL_CPUS // It is said that we should start core1 after all core0 launched /* becase optimize_link_coherent_ht is moved out from setup_coherent_ht_domain, * So here need to make sure last core0 is started, esp for two way system, * (there may be apic id conflicts in that case) */ start_other_cores(); wait_all_other_cores_started(bsp_apicid); #endif /* it will set up chains and store link pair for optimization later */ ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn bcm5785_early_setup(); #if CONFIG_SET_FIDVID { msr_t msr; msr=rdmsr(0xc0010042); printk(BIOS_DEBUG, "begin msr fid, vid %08x %08x\n", msr.hi, msr.lo); } enable_fid_change(); enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn); init_fidvid_bsp(bsp_apicid); // show final fid and vid { msr_t msr; msr=rdmsr(0xc0010042); printk(BIOS_DEBUG, "end msr fid, vid %08x %08x\n", msr.hi, msr.lo); } #endif needs_reset = optimize_link_coherent_ht(); needs_reset |= optimize_link_incoherent_ht(sysinfo); // fidvid change will issue one LDTSTOP and the HT change will be effective too if (needs_reset) { printk(BIOS_INFO, "ht reset -\n"); soft_reset(); } allow_all_aps_stop(bsp_apicid); //It's the time to set ctrl in sysinfo now; fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr); enable_smbus(); //do we need apci timer, tsc...., only debug need it for better output /* all ap stopped? */ // init_timer(); // Need to use TMICT to synchronize FID/VID sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo); post_cache_as_ram(); }