void vcpu_write_spsr32(struct kvm_vcpu *vcpu, unsigned long v) { int spsr_idx = vcpu_spsr32_mode(vcpu); if (!vcpu->arch.sysregs_loaded_on_cpu) { vcpu_gp_regs(vcpu)->spsr[spsr_idx] = v; return; } switch (spsr_idx) { case KVM_SPSR_SVC: write_sysreg_el1(v, spsr); case KVM_SPSR_ABT: write_sysreg(v, spsr_abt); case KVM_SPSR_UND: write_sysreg(v, spsr_und); case KVM_SPSR_IRQ: write_sysreg(v, spsr_irq); case KVM_SPSR_FIQ: write_sysreg(v, spsr_fiq); } }
static void __hyp_text __sysreg_restore_state(struct kvm_cpu_context *ctxt) { write_sysreg(ctxt->sys_regs[MPIDR_EL1], vmpidr_el2); write_sysreg(ctxt->sys_regs[CSSELR_EL1], csselr_el1); write_sysreg_el1(ctxt->sys_regs[SCTLR_EL1], sctlr); write_sysreg_el1(ctxt->sys_regs[CPACR_EL1], cpacr); write_sysreg_el1(ctxt->sys_regs[TTBR0_EL1], ttbr0); write_sysreg_el1(ctxt->sys_regs[TTBR1_EL1], ttbr1); write_sysreg_el1(ctxt->sys_regs[TCR_EL1], tcr); write_sysreg_el1(ctxt->sys_regs[ESR_EL1], esr); write_sysreg_el1(ctxt->sys_regs[AFSR0_EL1], afsr0); write_sysreg_el1(ctxt->sys_regs[AFSR1_EL1], afsr1); write_sysreg_el1(ctxt->sys_regs[FAR_EL1], far); write_sysreg_el1(ctxt->sys_regs[MAIR_EL1], mair); write_sysreg_el1(ctxt->sys_regs[VBAR_EL1], vbar); write_sysreg_el1(ctxt->sys_regs[CONTEXTIDR_EL1],contextidr); write_sysreg_el1(ctxt->sys_regs[AMAIR_EL1], amair); write_sysreg_el1(ctxt->sys_regs[CNTKCTL_EL1], cntkctl); write_sysreg(ctxt->sys_regs[PAR_EL1], par_el1); write_sysreg(ctxt->sys_regs[TPIDR_EL1], tpidr_el1); write_sysreg(ctxt->gp_regs.sp_el1, sp_el1); write_sysreg_el1(ctxt->gp_regs.elr_el1, elr); write_sysreg_el1(ctxt->gp_regs.spsr[KVM_SPSR_EL1],spsr); write_sysreg_el2(ctxt->gp_regs.regs.pc, elr); write_sysreg_el2(ctxt->gp_regs.regs.pstate, spsr); if (cpus_have_const_cap(ARM64_HAS_RAS_EXTN)) write_sysreg_s(ctxt->sys_regs[DISR_EL1], SYS_VDISR_EL2); }