static int check_all_flags( void )
{
int ret = 0;
int cpu0 = 0, cpu1 = 0;
#ifdef HAVE_MMX
if( x264_cpu_detect() & X264_CPU_MMXEXT )
{
ret |= add_flags( &cpu0, &cpu1, X264_CPU_MMX | X264_CPU_MMXEXT, "MMX" );
ret |= add_flags( &cpu0, &cpu1, X264_CPU_CACHELINE_64, "MMX Cache64" );
cpu1 &= ~X264_CPU_CACHELINE_64;
#ifdef ARCH_X86
ret |= add_flags( &cpu0, &cpu1, X264_CPU_CACHELINE_32, "MMX Cache32" );
cpu1 &= ~X264_CPU_CACHELINE_32;
#endif
}
if( x264_cpu_detect() & X264_CPU_SSE2 )
{
ret |= add_flags( &cpu0, &cpu1, X264_CPU_SSE | X264_CPU_SSE2 | X264_CPU_SSE2_IS_SLOW, "SSE2Slow" );
ret |= add_flags( &cpu0, &cpu1, X264_CPU_SSE2_IS_FAST, "SSE2Fast" );
ret |= add_flags( &cpu0, &cpu1, X264_CPU_CACHELINE_64, "SSE2Fast Cache64" );
}
if( x264_cpu_detect() & X264_CPU_SSE3 )
ret |= add_flags( &cpu0, &cpu1, X264_CPU_SSE3 | X264_CPU_CACHELINE_64, "SSE3" );
if( x264_cpu_detect() & X264_CPU_SSSE3 )
{
cpu1 &= ~X264_CPU_CACHELINE_64;
ret |= add_flags( &cpu0, &cpu1, X264_CPU_SSSE3, "SSSE3" );
ret |= add_flags( &cpu0, &cpu1, X264_CPU_CACHELINE_64, "SSSE3 Cache64" );
ret |= add_flags( &cpu0, &cpu1, X264_CPU_PHADD_IS_FAST, "PHADD" );
}
#elif ARCH_PPC
if( x264_cpu_detect() & X264_CPU_ALTIVEC )
{
fprintf( stderr, "x264: ALTIVEC against C\n" );
ret = check_all_funcs( 0, X264_CPU_ALTIVEC );
}
#endif
return ret;
}
// CPU dispatcher function
void __intel_cpu_indicator_init( void )
{
unsigned int cpu = x264_cpu_detect();
if( cpu&X264_CPU_AVX )
__intel_cpu_indicator = 0x20000;
else if( cpu&X264_CPU_SSE42 )
__intel_cpu_indicator = 0x8000;
else if( cpu&X264_CPU_SSE4 )
__intel_cpu_indicator = 0x2000;
else if( cpu&X264_CPU_SSSE3 )
__intel_cpu_indicator = 0x1000;
else if( cpu&X264_CPU_SSE3 )
__intel_cpu_indicator = 0x800;
else if( cpu&X264_CPU_SSE2 && !(cpu&X264_CPU_SSE2_IS_SLOW) )
__intel_cpu_indicator = 0x200;
else if( cpu&X264_CPU_SSE )
__intel_cpu_indicator = 0x80;
else if( cpu&X264_CPU_MMX2 )
__intel_cpu_indicator = 8;
else
__intel_cpu_indicator = 1;
}
