static void xhci_init(device_t dev) { struct soc_intel_baytrail_config *config = dev->chip_info; struct reg_script xhci_hc_init[] = { /* Initialize clock gating */ REG_SCRIPT_NEXT(xhci_clock_gating_script), /* Finalize XHCC1 and XHCC2 */ REG_PCI_RMW32(0x44, ~0x00000000, 0x83c00000), REG_PCI_RMW32(0x40, ~0x00800000, 0x80000000), /* Set USB2 Port Routing Mask */ REG_PCI_WRITE32(XHCI_USB2PRM, BYTM_USB2_PORT_MAP), /* Set USB3 Port Routing Mask */ REG_PCI_WRITE32(XHCI_USB3PRM, BYTM_USB3_PORT_MAP), /* * Disable ports if requested */ /* Open per-port disable control override */ REG_IO_RMW16(ACPI_BASE_ADDRESS + UPRWC, ~0, UPRWC_WR_EN), REG_PCI_WRITE32(XHCI_USB2PDO, config->usb2_port_disable_mask), REG_PCI_WRITE32(XHCI_USB3PDO, config->usb3_port_disable_mask), /* Close per-port disable control override */ REG_IO_RMW16(ACPI_BASE_ADDRESS + UPRWC, ~UPRWC_WR_EN, 0), REG_SCRIPT_END }; /* Initialize XHCI controller for boot or resume path */ if (acpi_is_wakeup_s3()) reg_script_run_on_dev(dev, xhci_init_resume_script); else reg_script_run_on_dev(dev, xhci_init_boot_script); /* C0 steppings change iCLK/USB PLL VCO settings from 5 to 7 */ if (pattrs_get()->stepping == STEP_C0) { uint32_t reg = iosf_ushphy_read(USHPHY_CDN_PLL_CONTROL); reg |= 0x00700000; iosf_ushphy_write(USHPHY_CDN_PLL_CONTROL, reg); } /* Finalize Initialization */ reg_script_run_on_dev(dev, xhci_hc_init); /* Route all ports to XHCI if requested */ if (config->usb_route_to_xhci) xhci_route_all(dev); }
static void xhci_init(device_t dev) { struct soc_intel_baytrail_config *config = dev->chip_info; struct reg_script xhci_hc_init[] = { /* Initialize clock gating */ REG_SCRIPT_NEXT(xhci_clock_gating_script), /* Finalize XHCC1 and XHCC2 */ REG_PCI_RMW32(0x44, ~0x00000000, 0x83c00000), REG_PCI_RMW32(0x40, ~0x00800000, 0x80000000), /* Set USB2 Port Routing Mask */ REG_PCI_WRITE32(XHCI_USB2PRM, BYTM_USB2_PORT_MAP), /* Set USB3 Port Routing Mask */ REG_PCI_WRITE32(XHCI_USB3PRM, BYTM_USB3_PORT_MAP), /* * Disable ports if requested */ /* Open per-port disable control override */ REG_IO_RMW16(ACPI_BASE_ADDRESS + UPRWC, ~0, UPRWC_WR_EN), REG_PCI_WRITE32(XHCI_USB2PDO, config->usb2_port_disable_mask), REG_PCI_WRITE32(XHCI_USB3PDO, config->usb3_port_disable_mask), /* Close per-port disable control override */ REG_IO_RMW16(ACPI_BASE_ADDRESS + UPRWC, ~UPRWC_WR_EN, 0), REG_SCRIPT_END }; /* Initialize XHCI controller for boot or resume path */ if (acpi_slp_type == 3) reg_script_run_on_dev(dev, xhci_init_resume_script); else reg_script_run_on_dev(dev, xhci_init_boot_script); /* Finalize Initialization */ reg_script_run_on_dev(dev, xhci_hc_init); /* Route all ports to XHCI if requested */ if (config->usb_route_to_xhci) xhci_route_all(dev); }