/* * Stops transfer processing for an endpoint and throws away all unprocessed * TRBs by setting the xHC's dequeue pointer to our enqueue pointer. The next * xhci_bulk_tx/xhci_ctrl_tx on this enpoint will add new transfers there and * ring the doorbell, causing this endpoint to start working again. * (Careful: This will BUG() when there was no transfer in progress. Shouldn't * happen in practice for current uses and is too complicated to fix right now.) */ static void abort_td(struct usb_device *udev, int ep_index) { struct xhci_ctrl *ctrl = udev->controller; struct xhci_ring *ring = ctrl->devs[udev->slot_id]->eps[ep_index].ring; union xhci_trb *event; u32 field; xhci_queue_command(ctrl, NULL, udev->slot_id, ep_index, TRB_STOP_RING); event = xhci_wait_for_event(ctrl, TRB_TRANSFER); field = le32_to_cpu(event->trans_event.flags); BUG_ON(TRB_TO_SLOT_ID(field) != udev->slot_id); BUG_ON(TRB_TO_EP_INDEX(field) != ep_index); BUG_ON(GET_COMP_CODE(le32_to_cpu(event->trans_event.transfer_len != COMP_STOP))); xhci_acknowledge_event(ctrl); event = xhci_wait_for_event(ctrl, TRB_COMPLETION); BUG_ON(TRB_TO_SLOT_ID(le32_to_cpu(event->event_cmd.flags)) != udev->slot_id || GET_COMP_CODE(le32_to_cpu( event->event_cmd.status)) != COMP_SUCCESS); xhci_acknowledge_event(ctrl); xhci_queue_command(ctrl, (void *)((uintptr_t)ring->enqueue | ring->cycle_state), udev->slot_id, ep_index, TRB_SET_DEQ); event = xhci_wait_for_event(ctrl, TRB_COMPLETION); BUG_ON(TRB_TO_SLOT_ID(le32_to_cpu(event->event_cmd.flags)) != udev->slot_id || GET_COMP_CODE(le32_to_cpu( event->event_cmd.status)) != COMP_SUCCESS); xhci_acknowledge_event(ctrl); }
static unsigned long xhci_wait_for_event_type(xhci_t *const xhci, const int trb_type, unsigned long *const timeout_us) { while (xhci_wait_for_event(&xhci->er, timeout_us)) { if (TRB_GET(TT, xhci->er.cur) == trb_type) break; xhci_handle_event(xhci); } return *timeout_us; }
static int xhci_hub_finish_port_reset(struct xhci_hcd *xhci, int port) { struct xhci_virtual_device *vdev; union xhci_trb trb; int ret; ret = xhci_wait_for_event(xhci, TRB_PORT_STATUS, &trb); if (ret) return ret; /* Reset any attached virtual devices */ list_for_each_entry(vdev, &xhci->vdev_list, list) if (vdev->udev && vdev->udev->portnr == port) xhci_virtdev_reset(vdev); return 0; }
/** * Queues up the Control Transfer Request * * @param udev pointer to the USB device structure * @param pipe contains the DIR_IN or OUT , devnum * @param req request type * @param length length of the buffer * @param buffer buffer to be read/written based on the request * @return returns 0 if successful else error code on failure */ int xhci_ctrl_tx(struct usb_device *udev, unsigned long pipe, struct devrequest *req, int length, void *buffer) { int ret; int start_cycle; int num_trbs; u32 field; u32 length_field; u64 buf_64 = 0; struct xhci_generic_trb *start_trb; struct xhci_ctrl *ctrl = udev->controller; int slot_id = udev->slot_id; int ep_index; u32 trb_fields[4]; struct xhci_virt_device *virt_dev = ctrl->devs[slot_id]; struct xhci_ring *ep_ring; union xhci_trb *event; XHCI_RING_PRINTF("req=%u (%#x), type=%u (%#x), value=%u (%#x), index=%u\n", req->request, req->request, req->requesttype, req->requesttype, le16_to_cpu(req->value), le16_to_cpu(req->value), le16_to_cpu(req->index)); ep_index = usb_pipe_ep_index(pipe); ep_ring = virt_dev->eps[ep_index].ring; /* * Check to see if the max packet size for the default control * endpoint changed during FS device enumeration */ if (udev->speed == USB_SPEED_FULL) { ret = xhci_check_maxpacket(udev); if (ret < 0) return ret; } xhci_inval_cache((uint32_t)virt_dev->out_ctx->bytes, virt_dev->out_ctx->size); struct xhci_ep_ctx *ep_ctx = NULL; ep_ctx = xhci_get_ep_ctx(ctrl, virt_dev->out_ctx, ep_index); /* 1 TRB for setup, 1 for status */ num_trbs = 2; /* * Don't need to check if we need additional event data and normal TRBs, * since data in control transfers will never get bigger than 16MB * XXX: can we get a buffer that crosses 64KB boundaries? */ if (length > 0) num_trbs++; /* * XXX: Calling routine prepare_ring() called in place of * prepare_trasfer() as there in 'Linux' since we are not * maintaining multiple TDs/transfer at the same time. */ ret = prepare_ring(ctrl, ep_ring, le32_to_cpu(ep_ctx->ep_info) & EP_STATE_MASK); if (ret < 0) return ret; /* * Don't give the first TRB to the hardware (by toggling the cycle bit) * until we've finished creating all the other TRBs. The ring's cycle * state may change as we enqueue the other TRBs, so save it too. */ start_trb = &ep_ring->enqueue->generic; start_cycle = ep_ring->cycle_state; XHCI_RING_PRINTF("start_trb %p, start_cycle %d\n", start_trb, start_cycle); /* Queue setup TRB - see section 6.4.1.2.1 */ /* FIXME better way to translate setup_packet into two u32 fields? */ field = 0; field |= TRB_IDT | (TRB_SETUP << TRB_TYPE_SHIFT); if (start_cycle == 0) field |= 0x1; /* xHCI 1.0 6.4.1.2.1: Transfer Type field */ //if (HC_VERSION(xhci_readl(&ctrl->hccr->cr_capbase)) == 0x100) { // XHCI_MTK if (1) { if (length > 0) { if (req->requesttype & USB_DIR_IN) field |= (TRB_DATA_IN << TRB_TX_TYPE_SHIFT); else field |= (TRB_DATA_OUT << TRB_TX_TYPE_SHIFT); } } XHCI_RING_PRINTF("req->requesttype = %d, req->request = %d," "le16_to_cpu(req->value) = %d," "le16_to_cpu(req->index) = %d," "le16_to_cpu(req->length) = %d\n", req->requesttype, req->request, le16_to_cpu(req->value), le16_to_cpu(req->index), le16_to_cpu(req->length)); trb_fields[0] = req->requesttype | req->request << 8 | le16_to_cpu(req->value) << 16; trb_fields[1] = le16_to_cpu(req->index) | le16_to_cpu(req->length) << 16; /* TRB_LEN | (TRB_INTR_TARGET) */ trb_fields[2] = (8 | ((0 & TRB_INTR_TARGET_MASK) << TRB_INTR_TARGET_SHIFT)); /* Immediate data in pointer */ trb_fields[3] = field; queue_trb(ctrl, ep_ring, true, trb_fields); /* Re-initializing field to zero */ field = 0; /* If there's data, queue data TRBs */ /* Only set interrupt on short packet for IN endpoints */ if (usb_pipein(pipe)) field = TRB_ISP | (TRB_DATA << TRB_TYPE_SHIFT); else field = (TRB_DATA << TRB_TYPE_SHIFT); length_field = (length & TRB_LEN_MASK) | 0 | //length_field = (length & TRB_LEN_MASK) | xhci_td_remainder(length) | ((0 & TRB_INTR_TARGET_MASK) << TRB_INTR_TARGET_SHIFT); //XHCI_RING_PRINTF("length_field = %d, length = %d," // "xhci_td_remainder(length) = %d , TRB_INTR_TARGET(0) = %d\n", // length_field, (length & TRB_LEN_MASK), // xhci_td_remainder(length), 0); if (length > 0) { if (req->requesttype & USB_DIR_IN) field |= TRB_DIR_IN; buf_64 = (uintptr_t)buffer; trb_fields[0] = lower_32_bits(buf_64); trb_fields[1] = upper_32_bits(buf_64); trb_fields[2] = length_field; trb_fields[3] = field | ep_ring->cycle_state; xhci_flush_cache((uint32_t)buffer, length); queue_trb(ctrl, ep_ring, true, trb_fields); } /* * Queue status TRB - * see Table 7 and sections 4.11.2.2 and 6.4.1.2.3 */ /* If the device sent data, the status stage is an OUT transfer */ field = 0; if (length > 0 && req->requesttype & USB_DIR_IN) field = 0; else field = TRB_DIR_IN; trb_fields[0] = 0; trb_fields[1] = 0; trb_fields[2] = ((0 & TRB_INTR_TARGET_MASK) << TRB_INTR_TARGET_SHIFT); /* Event on completion */ trb_fields[3] = field | TRB_IOC | (TRB_STATUS << TRB_TYPE_SHIFT) | ep_ring->cycle_state; queue_trb(ctrl, ep_ring, false, trb_fields); giveback_first_trb(udev, ep_index, start_cycle, start_trb); event = xhci_wait_for_event(ctrl, TRB_TRANSFER); if (!event) goto abort; field = le32_to_cpu(event->trans_event.flags); BUG_ON(TRB_TO_SLOT_ID(field) != slot_id); BUG_ON(TRB_TO_EP_INDEX(field) != ep_index); record_transfer_result(udev, event, length); xhci_acknowledge_event(ctrl); /* Invalidate buffer to make it available to usb-core */ if (length > 0) xhci_inval_cache((uint32_t)buffer, length); if (GET_COMP_CODE(le32_to_cpu(event->trans_event.transfer_len)) == COMP_SHORT_TX) { /* Short data stage, clear up additional status stage event */ event = xhci_wait_for_event(ctrl, TRB_TRANSFER); if (!event) goto abort; BUG_ON(TRB_TO_SLOT_ID(field) != slot_id); BUG_ON(TRB_TO_EP_INDEX(field) != ep_index); xhci_acknowledge_event(ctrl); } return (udev->status != USB_ST_NOT_PROC) ? 0 : -1; abort: XHCI_RING_PRINTF("XHCI control transfer timed out, aborting...\n"); abort_td(udev, ep_index); udev->status = USB_ST_NAK_REC; udev->act_len = 0; return -ETIMEDOUT; }
/** * Queues up the BULK Request * * @param udev pointer to the USB device structure * @param pipe contains the DIR_IN or OUT , devnum * @param length length of the buffer * @param buffer buffer to be read/written based on the request * @return returns 0 if successful else -1 on failure */ int xhci_bulk_tx(struct usb_device *udev, unsigned long pipe, int length, void *buffer) { int num_trbs = 0; struct xhci_generic_trb *start_trb; int first_trb = 0; int start_cycle; u32 field = 0; u32 length_field = 0; struct xhci_ctrl *ctrl = udev->controller; int slot_id = udev->slot_id; int ep_index; struct xhci_virt_device *virt_dev; struct xhci_ep_ctx *ep_ctx; struct xhci_ring *ring; /* EP transfer ring */ union xhci_trb *event; int running_total, trb_buff_len; unsigned int total_packet_count; int maxpacketsize; u64 addr; int ret; u32 trb_fields[4]; u64 val_64 = (uintptr_t)KSEG1ADDR(buffer); XHCI_RING_PRINTF("dev=%p, pipe=%lx, buffer=%p, length=%d\n", udev, pipe, buffer, length); ep_index = usb_pipe_ep_index(pipe); virt_dev = ctrl->devs[slot_id]; xhci_inval_cache((uint32_t)virt_dev->out_ctx->bytes, virt_dev->out_ctx->size); ep_ctx = xhci_get_ep_ctx(ctrl, virt_dev->out_ctx, ep_index); ring = virt_dev->eps[ep_index].ring; /* * How much data is (potentially) left before the 64KB boundary? * XHCI Spec puts restriction( TABLE 49 and 6.4.1 section of XHCI Spec) * that the buffer should not span 64KB boundary. if so * we send request in more than 1 TRB by chaining them. */ running_total = TRB_MAX_BUFF_SIZE - (lower_32_bits(val_64) & (TRB_MAX_BUFF_SIZE - 1)); trb_buff_len = running_total; running_total &= TRB_MAX_BUFF_SIZE - 1; /* * If there's some data on this 64KB chunk, or we have to send a * zero-length transfer, we need at least one TRB */ if (running_total != 0 || length == 0) num_trbs++; /* How many more 64KB chunks to transfer, how many more TRBs? */ while (running_total < length) { num_trbs++; running_total += TRB_MAX_BUFF_SIZE; } /* * XXX: Calling routine prepare_ring() called in place of * prepare_trasfer() as there in 'Linux' since we are not * maintaining multiple TDs/transfer at the same time. */ ret = prepare_ring(ctrl, ring, le32_to_cpu(ep_ctx->ep_info) & EP_STATE_MASK); if (ret < 0) return ret; /* * Don't give the first TRB to the hardware (by toggling the cycle bit) * until we've finished creating all the other TRBs. The ring's cycle * state may change as we enqueue the other TRBs, so save it too. */ start_trb = &ring->enqueue->generic; start_cycle = ring->cycle_state; running_total = 0; maxpacketsize = usb_maxpacket(udev, pipe); total_packet_count = DIV_ROUND_UP(length, maxpacketsize); /* How much data is in the first TRB? */ /* * How much data is (potentially) left before the 64KB boundary? * XHCI Spec puts restriction( TABLE 49 and 6.4.1 section of XHCI Spec) * that the buffer should not span 64KB boundary. if so * we send request in more than 1 TRB by chaining them. */ addr = KSEG1ADDR(val_64); if (trb_buff_len > length) trb_buff_len = length; first_trb = true; /* flush the buffer before use */ xhci_flush_cache((uint32_t)buffer, length); /* Queue the first TRB, even if it's zero-length */ do { u32 remainder = 0; field = 0; /* Don't change the cycle bit of the first TRB until later */ if (first_trb) { first_trb = false; if (start_cycle == 0) field |= TRB_CYCLE; } else { field |= ring->cycle_state; } /* * Chain all the TRBs together; clear the chain bit in the last * TRB to indicate it's the last TRB in the chain. */ if (num_trbs > 1) field |= TRB_CHAIN; else field |= TRB_IOC; /* Only set interrupt on short packet for IN endpoints */ if (usb_pipein(pipe)) field |= TRB_ISP; /* Set the TRB length, TD size, and interrupter fields. */ if (HC_VERSION(xhci_readl(&ctrl->hccr->cr_capbase)) < 0x100) remainder = xhci_td_remainder(length, running_total, maxpacketsize, trb_buff_len); //remainder = xhci_td_remainder(length - running_total); else remainder = xhci_v1_0_td_remainder(running_total, trb_buff_len, total_packet_count, maxpacketsize, num_trbs - 1); length_field = ((trb_buff_len & TRB_LEN_MASK) | remainder | ((0 & TRB_INTR_TARGET_MASK) << TRB_INTR_TARGET_SHIFT)); trb_fields[0] = lower_32_bits(addr); trb_fields[1] = upper_32_bits(addr); trb_fields[2] = length_field; trb_fields[3] = field | (TRB_NORMAL << TRB_TYPE_SHIFT); queue_trb(ctrl, ring, (num_trbs > 1), trb_fields); --num_trbs; running_total += trb_buff_len; /* Calculate length for next transfer */ addr += trb_buff_len; trb_buff_len = min((length - running_total), TRB_MAX_BUFF_SIZE); } while (running_total < length); giveback_first_trb(udev, ep_index, start_cycle, start_trb); event = xhci_wait_for_event(ctrl, TRB_TRANSFER); if (!event) { XHCI_RING_PRINTF("XHCI bulk transfer timed out, aborting...\n"); abort_td(udev, ep_index); udev->status = USB_ST_NAK_REC; /* closest thing to a timeout */ udev->act_len = 0; return -ETIMEDOUT; } field = le32_to_cpu(event->trans_event.flags); BUG_ON(TRB_TO_SLOT_ID(field) != slot_id); BUG_ON(TRB_TO_EP_INDEX(field) != ep_index); BUG_ON(*(void **)(uintptr_t)le64_to_cpu(event->trans_event.buffer) - buffer > (size_t)length); record_transfer_result(udev, event, length); xhci_acknowledge_event(ctrl); xhci_inval_cache((uint32_t)buffer, length); return (udev->status != USB_ST_NOT_PROC) ? 0 : -1; }