/** * xilinx_drm_plane_update_prio - Configure plane priorities based on zpos * @manager: the plane manager * * Z-position values are user requested position of planes. The priority is * the actual position of planes in hardware. Some hardware doesn't allow * any duplicate priority, so this function needs to be called when a duplicate * priority is found. Then planes are sorted by zpos value, and the priorities * are reconfigured. A plane with lower plane ID gets assigned to the lower * priority when planes have the same zpos value. */ static void xilinx_drm_plane_update_prio(struct xilinx_drm_plane_manager *manager) { struct xilinx_drm_plane *planes[MAX_PLANES]; struct xilinx_drm_plane *plane; unsigned int i, j; /* sort planes by zpos */ for (i = 0; i < manager->num_planes; i++) { plane = manager->planes[i]; for (j = i; j > 0; --j) { if (planes[j - 1]->zpos <= plane->zpos) break; planes[j] = planes[j - 1]; } planes[j] = plane; } xilinx_osd_disable_rue(manager->osd); /* remove duplicates by reassigning priority */ for (i = 0; i < manager->num_planes; i++) { planes[i]->prio = i; xilinx_osd_layer_set_priority(planes[i]->osd_layer, planes[i]->prio); } xilinx_osd_enable_rue(manager->osd); }
/** * xilinx_drm_plane_manager_dpms - Set DPMS for the Xilinx plane manager * @manager: Xilinx plane manager object * @dpms: requested DPMS * * Set the Xilinx plane manager to the given DPMS state. This function is * usually called from the CRTC driver with calling xilinx_drm_plane_dpms(). */ void xilinx_drm_plane_manager_dpms(struct xilinx_drm_plane_manager *manager, int dpms) { switch (dpms) { case DRM_MODE_DPMS_ON: if (manager->dp_sub) { xilinx_drm_dp_sub_set_bg_color(manager->dp_sub, 0, 0, 0); xilinx_drm_dp_sub_enable(manager->dp_sub); } if (manager->osd) { xilinx_osd_disable_rue(manager->osd); xilinx_osd_enable(manager->osd); xilinx_osd_enable_rue(manager->osd); } break; default: if (manager->osd) xilinx_osd_reset(manager->osd); if (manager->dp_sub) xilinx_drm_dp_sub_disable(manager->dp_sub); break; } }
/* mode set a plane */ int xilinx_drm_plane_mode_set(struct drm_plane *base_plane, struct drm_framebuffer *fb, int crtc_x, int crtc_y, unsigned int crtc_w, unsigned int crtc_h, uint32_t src_x, uint32_t src_y, uint32_t src_w, uint32_t src_h) { struct xilinx_drm_plane *plane = to_xilinx_plane(base_plane); struct drm_gem_cma_object *obj; size_t offset; unsigned int hsub, vsub, i; DRM_DEBUG_KMS("plane->id: %d\n", plane->id); if (fb->pixel_format != plane->format) { DRM_ERROR("unsupported pixel format %08x\n", fb->pixel_format); return -EINVAL; } /* configure cresample */ if (plane->cresample) xilinx_cresample_configure(plane->cresample, crtc_w, crtc_h); /* configure rgb2yuv */ if (plane->rgb2yuv) xilinx_rgb2yuv_configure(plane->rgb2yuv, crtc_w, crtc_h); DRM_DEBUG_KMS("h: %d(%d), v: %d(%d)\n", src_w, crtc_x, src_h, crtc_y); DRM_DEBUG_KMS("bpp: %d\n", fb->bits_per_pixel / 8); hsub = drm_format_horz_chroma_subsampling(fb->pixel_format); vsub = drm_format_vert_chroma_subsampling(fb->pixel_format); for (i = 0; i < drm_format_num_planes(fb->pixel_format); i++) { unsigned int width = src_w / (i ? hsub : 1); unsigned int height = src_h / (i ? vsub : 1); unsigned int cpp = drm_format_plane_cpp(fb->pixel_format, i); obj = xilinx_drm_fb_get_gem_obj(fb, i); if (!obj) { DRM_ERROR("failed to get a gem obj for fb\n"); return -EINVAL; } plane->dma[i].xt.numf = height; plane->dma[i].sgl[0].size = width * cpp; plane->dma[i].sgl[0].icg = fb->pitches[i] - plane->dma[i].sgl[0].size; offset = src_x * cpp + src_y * fb->pitches[i]; offset += fb->offsets[i]; plane->dma[i].xt.src_start = obj->paddr + offset; plane->dma[i].xt.frame_size = 1; plane->dma[i].xt.dir = DMA_MEM_TO_DEV; plane->dma[i].xt.src_sgl = true; plane->dma[i].xt.dst_sgl = false; plane->dma[i].is_active = true; } for (; i < MAX_NUM_SUB_PLANES; i++) plane->dma[i].is_active = false; /* set OSD dimensions */ if (plane->manager->osd) { xilinx_osd_disable_rue(plane->manager->osd); xilinx_osd_layer_set_dimension(plane->osd_layer, crtc_x, crtc_y, src_w, src_h); xilinx_osd_enable_rue(plane->manager->osd); } if (plane->manager->dp_sub) { int ret; ret = xilinx_drm_dp_sub_layer_check_size(plane->manager->dp_sub, plane->dp_layer, src_w, src_h); if (ret) return ret; } return 0; }
/* set plane dpms */ void xilinx_drm_plane_dpms(struct drm_plane *base_plane, int dpms) { struct xilinx_drm_plane *plane = to_xilinx_plane(base_plane); struct xilinx_drm_plane_manager *manager = plane->manager; unsigned int i; DRM_DEBUG_KMS("plane->id: %d\n", plane->id); DRM_DEBUG_KMS("dpms: %d -> %d\n", plane->dpms, dpms); if (plane->dpms == dpms) return; plane->dpms = dpms; switch (dpms) { case DRM_MODE_DPMS_ON: if (manager->dp_sub) { if (plane->primary) { xilinx_drm_dp_sub_enable_alpha(manager->dp_sub, plane->alpha_enable); xilinx_drm_dp_sub_set_alpha(manager->dp_sub, plane->alpha); } xilinx_drm_dp_sub_layer_enable(manager->dp_sub, plane->dp_layer); } /* start dma engine */ for (i = 0; i < MAX_NUM_SUB_PLANES; i++) if (plane->dma[i].chan && plane->dma[i].is_active) dma_async_issue_pending(plane->dma[i].chan); if (plane->rgb2yuv) xilinx_rgb2yuv_enable(plane->rgb2yuv); if (plane->cresample) xilinx_cresample_enable(plane->cresample); /* enable osd */ if (manager->osd) { xilinx_osd_disable_rue(manager->osd); xilinx_osd_layer_set_priority(plane->osd_layer, plane->prio); xilinx_osd_layer_enable_alpha(plane->osd_layer, plane->alpha_enable); xilinx_osd_layer_set_alpha(plane->osd_layer, plane->alpha); xilinx_osd_layer_enable(plane->osd_layer); xilinx_osd_enable_rue(manager->osd); } break; default: /* disable/reset osd */ if (manager->osd) { xilinx_osd_disable_rue(manager->osd); xilinx_osd_layer_set_dimension(plane->osd_layer, 0, 0, 0, 0); xilinx_osd_layer_disable(plane->osd_layer); xilinx_osd_enable_rue(manager->osd); } if (plane->cresample) { xilinx_cresample_disable(plane->cresample); xilinx_cresample_reset(plane->cresample); } if (plane->rgb2yuv) { xilinx_rgb2yuv_disable(plane->rgb2yuv); xilinx_rgb2yuv_reset(plane->rgb2yuv); } /* stop dma engine and release descriptors */ for (i = 0; i < MAX_NUM_SUB_PLANES; i++) { if (plane->dma[i].chan && plane->dma[i].is_active) { dmaengine_terminate_all(plane->dma[i].chan); plane->dma[i].is_active = false; } } if (manager->dp_sub) xilinx_drm_dp_sub_layer_disable(manager->dp_sub, plane->dp_layer); break; } }
/* mode set a plane */ int xilinx_drm_plane_mode_set(struct drm_plane *base_plane, struct drm_framebuffer *fb, int crtc_x, int crtc_y, unsigned int crtc_w, unsigned int crtc_h, uint32_t src_x, uint32_t src_y, uint32_t src_w, uint32_t src_h) { struct xilinx_drm_plane *plane = to_xilinx_plane(base_plane); struct drm_gem_cma_object *obj; size_t offset; DRM_DEBUG_KMS("plane->id: %d\n", plane->id); if (fb->pixel_format != plane->format) { DRM_ERROR("unsupported pixel format %08x\n", fb->pixel_format); return -EINVAL; } /* configure cresample */ if (plane->cresample) xilinx_cresample_configure(plane->cresample, crtc_w, crtc_h); /* configure rgb2yuv */ if (plane->rgb2yuv) xilinx_rgb2yuv_configure(plane->rgb2yuv, crtc_w, crtc_h); obj = drm_fb_cma_get_gem_obj(fb, 0); if (!obj) { DRM_ERROR("failed to get a gem obj for fb\n"); return -EINVAL; } DRM_DEBUG_KMS("h: %d(%d), v: %d(%d), paddr: %p\n", src_w, crtc_x, src_h, crtc_y, (void *)obj->paddr); DRM_DEBUG_KMS("bpp: %d\n", fb->bits_per_pixel / 8); /* configure dma desc */ plane->dma.xt.numf = src_h; plane->dma.sgl[0].size = src_w * fb->bits_per_pixel / 8; plane->dma.sgl[0].icg = fb->pitches[0] - plane->dma.sgl[0].size; offset = src_x * fb->bits_per_pixel / 8 + src_y * fb->pitches[0]; plane->dma.xt.src_start = obj->paddr + offset; plane->dma.xt.frame_size = 1; plane->dma.xt.dir = DMA_MEM_TO_DEV; plane->dma.xt.src_sgl = true; plane->dma.xt.dst_sgl = false; /* set OSD dimensions */ if (plane->manager->osd) { xilinx_osd_disable_rue(plane->manager->osd); /* if a plane is private, it's for crtc */ if (plane->priv) xilinx_osd_set_dimension(plane->manager->osd, crtc_w, crtc_h); xilinx_osd_layer_set_dimension(plane->osd_layer, crtc_x, crtc_y, src_w, src_h); xilinx_osd_enable_rue(plane->manager->osd); } return 0; }
/* set plane dpms */ void xilinx_drm_plane_dpms(struct drm_plane *base_plane, int dpms) { struct xilinx_drm_plane *plane = to_xilinx_plane(base_plane); struct xilinx_drm_plane_manager *manager = plane->manager; DRM_DEBUG_KMS("plane->id: %d\n", plane->id); DRM_DEBUG_KMS("dpms: %d -> %d\n", plane->dpms, dpms); if (plane->dpms == dpms) return; plane->dpms = dpms; switch (dpms) { case DRM_MODE_DPMS_ON: /* start dma engine */ dma_async_issue_pending(plane->dma.chan); if (plane->rgb2yuv) xilinx_rgb2yuv_enable(plane->rgb2yuv); if (plane->cresample) xilinx_cresample_enable(plane->cresample); /* enable osd */ if (manager->osd) { xilinx_osd_disable_rue(manager->osd); xilinx_osd_layer_set_priority(plane->osd_layer, plane->prio); xilinx_osd_layer_set_alpha(plane->osd_layer, 1, plane->alpha); xilinx_osd_layer_enable(plane->osd_layer); if (plane->priv) { /* set background color as black */ xilinx_osd_set_color(manager->osd, 0x0, 0x0, 0x0); xilinx_osd_enable(manager->osd); } xilinx_osd_enable_rue(manager->osd); } break; default: /* disable/reset osd */ if (manager->osd) { xilinx_osd_disable_rue(manager->osd); xilinx_osd_layer_set_dimension(plane->osd_layer, 0, 0, 0, 0); xilinx_osd_layer_disable(plane->osd_layer); if (plane->priv) xilinx_osd_reset(manager->osd); xilinx_osd_enable_rue(manager->osd); } if (plane->cresample) { xilinx_cresample_disable(plane->cresample); xilinx_cresample_reset(plane->cresample); } if (plane->rgb2yuv) { xilinx_rgb2yuv_disable(plane->rgb2yuv); xilinx_rgb2yuv_reset(plane->rgb2yuv); } /* stop dma engine and release descriptors */ dmaengine_terminate_all(plane->dma.chan); break; } }
/* mode set a plane */ int xilinx_drm_plane_mode_set(struct drm_plane *base_plane, struct drm_framebuffer *fb, int crtc_x, int crtc_y, unsigned int crtc_w, unsigned int crtc_h, uint32_t src_x, uint32_t src_y, uint32_t src_w, uint32_t src_h) { struct xilinx_drm_plane *plane = to_xilinx_plane(base_plane); struct drm_gem_cma_object *obj; DRM_DEBUG_KMS("plane->id: %d\n", plane->id); if (fb->pixel_format != plane->format) { DRM_ERROR("unsupported pixel format %08x\n", fb->pixel_format); return -EINVAL; } /* configure cresample */ if (plane->cresample) xilinx_cresample_configure(plane->cresample, crtc_w, crtc_h); /* configure rgb2yuv */ if (plane->rgb2yuv) xilinx_rgb2yuv_configure(plane->rgb2yuv, crtc_w, crtc_h); obj = drm_fb_cma_get_gem_obj(fb, 0); if (!obj) { DRM_ERROR("failed to get a gem obj for fb\n"); return -EINVAL; } plane->x = src_x; plane->y = src_y; plane->bpp = fb->bits_per_pixel / 8; plane->paddr = obj->paddr; DRM_DEBUG_KMS("h: %d(%d), v: %d(%d), paddr: %p\n", src_w, crtc_x, src_h, crtc_y, (void *)obj->paddr); DRM_DEBUG_KMS("bpp: %d\n", plane->bpp); /* configure vdma desc */ plane->vdma.dma_config.hsize = src_w * plane->bpp; plane->vdma.dma_config.vsize = src_h; plane->vdma.dma_config.stride = fb->pitches[0]; plane->vdma.dma_config.park = 1; plane->vdma.dma_config.park_frm = 0; dmaengine_device_control(plane->vdma.chan, DMA_SLAVE_CONFIG, (unsigned long)&plane->vdma.dma_config); /* set OSD dimensions */ if (plane->manager->osd) { xilinx_osd_disable_rue(plane->manager->osd); /* if a plane is private, it's for crtc */ if (plane->priv) xilinx_osd_set_dimension(plane->manager->osd, crtc_w, crtc_h); xilinx_osd_layer_set_dimension(plane->osd_layer, crtc_x, crtc_y, src_w, src_h); xilinx_osd_enable_rue(plane->manager->osd); } return 0; }